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| rev. 2.6 november 2000 1/140 this is preliminary information on a new product in development or undergoing evaluation. details are subject to change without notice. st72104g, st72215g, st72216g, st72254g 8-bit mcu with single voltage flash memory, adc, 16-bit timers, spi, i 2 c interfaces preliminary data n memories 4k or 8k bytes program memory (rom and single voltage flash) with read-out protec- tion and in-situ programming (remote isp) 256 bytes ram n clock, reset and supply management enhanced reset system enhanced low voltage supply supervisor with 3 programmable levels clock sources: crystal/ceramic resonator os- cillators or rc oscillators, external clock, backup clock security system clock-out capability 3 power saving modes: halt, wait and slow n interrupt management 7 interrupt vectors plus trap and reset 22 external interrupt lines (on 2 vectors) n 22 i/o ports 22 multifunctional bidirectional i/o lines 14 alternate function lines 8 high sink outputs n 3 timers configurable watchdog timer two 16-bit timers with: 2 input captures, 2 out- put compares, external clock input on one tim- er, pwm and pulse generator modes (one only on st72104gx and st72216g1) n 2 communications interfaces spi synchronous serial interface i2c multimaster interface (only on st72254gx) n 1 analog peripheral 8-bit adc with 6 input channels (except on st72104gx) n instruction set 8-bit data manipulation 63 basic instructions 17 main addressing modes 8 x 8 unsigned multiply instruction true bit manipulation n development tools full hardware/software development package device summary sdip32 so28 features st72104g1 st72104g2 st72216g1 st72215g2 st72254g1 st72254g2 program memory - bytes 4k 8k 4k 8k 4k 8k ram (stack) - bytes 256 (128) peripherals watchdog timer, one 16-bit timer, spi watchdog timer, one 16-bit timer, spi, adc watchdog timer, two 16-bit timers, spi, adc watchdog timer, two 16-bit timers, spi, i c, adc operating supply 3.2v to 5.5v cpu frequency up to 8 mhz (with oscillator up to 16 mhz) operating temperature 0 cto70 c / -10 c to +85 c (-40 c to +85 c / -40 c to105 c / -40 cto125 c optional) packages so28 / sdip32 1
table of contents 140 2/140 2 1 introduction . . . . . . . . . . . . . . . . . . . . . ......................................... 6 2 pin description . . . . . . . . . . . . ........................................... ..... 7 3 register & memory map . . . ............................. ................... 10 4 flash program memory . . . . . . . . . . . . . . . . . ................................. 13 4.1 introduction . ...................................................... 13 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 13 4.3 structural organisation . . . . . . . . . . . . . . . ........................... 13 4.4 in-situ programming (isp) mode . .................................... 13 4.5 memory read-out protection . . . . . ............................. .... 13 5 central processing unit . . ............................................... 14 5.1 introduction . ...................................................... 14 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 14 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . ................................. 14 6 central processing unit (cont'd) . . . . . . . . . ................................. 16 7 supply, reset and clock management . . . . ................................ 17 7.1 low voltage detector (lvd) . . . . . . . . ................................ 18 7.2 reset sequence manager (rsm) . . . . . ................................ 19 7.2.1 introduction . . . .................................................... 19 7.2.2 asynchronous external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 20 7.2.3 internal low voltage detection reset . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 20 7.2.4 internal watchdog reset . . . . . . . . . . .................................. 20 7.3 multi-oscillator (mo) . . . . . . . . . . . . . . . ................................ 21 7.4 clock security system (css) . . . . . . . . ................................ 22 7.4.1 clock filter control . . ........................................... .... 22 7.4.2 safe oscillator control . . . . ........................................... 22 7.4.3 low power modes . . ............................................... 22 7.4.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 22 7.5 clock reset and supply register description (crsr) . . . . . . . ........ 23 7.6 main clock controller (mcc) . . . . . . . . . . . . ........................... 24 8 interrupts . . ......................... .................................... 25 8.1 non maskable software interrupt . . . . . . ........................... 25 8.2 external interrupts . . . . . . . . . . . . . .................................. 25 8.3 peripheral interrupts . . ........................................... 25 9 power saving modes . . . . . . . . . . ........................................... 27 9.1 introduction . ...................................................... 27 9.2 slow mode . . . . . . . . . . . . . . ........................................... 27 9.3 wait mode . . . . . . . . . . . ............................................... 28 9.4 halt mode . . . . . . . . . . . ........................................... .... 29 10 i/o ports . . . .............................................................. 30 10.1 introduction . ...................................................... 30 10.2 functional description . . . . ........................................ 30 10.2.1input modes . . . . . . . . . . . . . . . . . . . . . . . ................................ 30 10.2.2output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table of contents 3/140 3 10.2.3alternate functions . . . . . . . . . . . . . . . . ................................. 30 10.3 i/o port implementation . . . . ........................................ 33 10.4 low power modes . . . . . . . . . . . . . . . . . ................................. 34 10.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 34 10.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 34 11 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.1 i/o port interrupt sensitivity . . . . . . ................................ 36 11.2 i/o port alternate functions . . . . . .................................. 36 11.3 miscellaneous register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12 on-chip peripherals . . . . . . ............................................... 39 12.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . ........................... 39 12.1.1introduction . . . . ................................................... 39 12.1.2main features . . . . . . . . . . . . . . . . . . . . ................................. 39 12.1.3functional description . . . . . . . ........................................ 39 12.1.4hardware watchdog option . . . . . . . . . . . ................................ 40 12.1.5low power modes . . . ........................................... .... 40 12.1.6interrupts . . . . . . . . . . . . . . . . . . . . . . . . . ................................ 40 12.1.7register description . . . . . . . . . ........................................ 40 12.2 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 42 12.2.1introduction . . . . ................................................... 42 12.2.2main features . . . . . . . . . . . . . . . . . . . . ................................. 42 12.2.3functional description . . . . . . . ........................................ 42 12.2.4low power modes . . ........................................... .... 54 12.2.5interrupts . . . . . . ................................................... 54 12.2.6summary of timer modes . . . . . . . . . . . . . . . . . ........................... 54 12.2.7register description . . . . . . . . . ........................................ 55 12.3 serial peripheral interface (spi) . .................................. 60 12.3.1introduction . . . . ................................................... 60 12.3.2main features . . . . . . . . . . . . . . . . . . . . ................................. 60 12.3.3general description . . . . . . ........................................... 60 12.3.4functional description . . . . . . . ........................................ 62 12.3.5low power modes . . . ........................................... .... 69 12.3.6interrupts . . . . . . ................................................... 69 12.3.7register description . . . . . . . . . ........................................ 70 12.4 i2c bus interface (i2c) . . . . . . . . . . ................................ .... 73 12.4.1introduction . . . . ................................................... 73 12.4.2main features . . . . . . . . . . . . . . . . . . . . ................................. 73 12.4.3general description . . . . . . . . . ........................................ 73 12.4.4functional description . . . . . . . ........................................ 75 12.4.5low power modes . . . ........................................... .... 79 12.4.6interrupts . . . . . . . . . . . . . . . . . . . . . . . . . ................................ 79 12.4.7register description . . . . . . . . . ........................................ 80 12.5 8-bit a/d converter (adc) ........................................... 86 12.5.1introduction . . . . ................................................... 86 12.5.2main features . . . . . . . . . . . . . . . . . . . . ................................. 86 12.5.3functional description . . . . . . . ........................................ 86 table of contents 140 4/140 12.5.4low power modes . . ........................................... .... 87 12.5.5interrupts . . . . . . . . . . . . . . . . . . . . . . . . . ................................ 87 12.5.6register description . . . . . . . . . ........................................ 88 13 instruction set . . . . . . . . . . . . . . . . . . . . . . . . ............................. .... 90 13.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 13.1.1inherent . . . . . . . . . . . . . . . . . . . . . . . . . ................................. 91 13.1.2immediate . . .................. .................................... 91 13.1.3direct . ........................................................... 91 13.1.4indexed (no offset, short, long) . . . . . .................................. 91 13.1.5indirect (short, long) . . . . . ........................................... 91 13.1.6indirect indexed (short, long) . ........................................ 92 13.1.7relative mode (direct, indirect) . . . . ................................ .... 92 13.2 instruction groups . . . . . . . . . . . . . . . . . . .............................. 93 14 electrical characteristics . . . . ......................................... 96 14.1 parameter conditions . . . . . . . . . . . . . . . . .............................. 96 14.1.1minimum and maximum values ........................................ 96 14.1.2typical values . . . . . . . . . . ........................................... 96 14.1.3typical curves . . . . . . . . . . . . . ........................................ 96 14.1.4loading capacitor . . . . . . . . . . . . . . . . . .................................. 96 14.1.5pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.2.1voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.2.2current characteristics . . . . . . . . . . . . . . . . .............................. 97 14.2.3thermal characteristics . . . . . . . . . .................................... 97 14.3 operating conditions . . . . . . . . . . .................................... 98 14.3.1general operating conditions . . . . .................................... 98 14.3.2operating conditions with low voltage detector (lvd) . ................... 100 14.4 supply current characteristics . . . ............................... 102 14.4.1run and slow modes . . . . . ....................................... 102 14.4.2wait and slow wait modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 103 14.4.3halt mode . . . . . . . . .............................................. 104 14.4.4supply and clock managers . ........................................ 104 14.4.5on-chip peripherals . . . . . .......................................... 104 14.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . .......... 105 14.5.1general timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 14.5.2external clock source . . . . . . ....................................... 105 14.5.3crystal and ceramic resonator oscillators . . . . .......................... 106 14.5.4rc oscillators . . . . . . . . . . .......................................... 110 14.5.5clock security system (css) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 14.6 memory characteristics . . . ....................................... 112 14.6.1ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . .............. 112 14.6.2flash program memory . . . . ....................................... 112 14.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14.7.1functional ems . . . . . .............................................. 113 14.7.2absolute electrical sensitivity . . . . . . . . . . . . . . .......................... 114 14.7.3esd pin protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 14.8 i/o port pin characteristics ....................................... 118 table of contents 5/140 14.8.1general characteristics . . . . . . . . . . . . ................................. 118 14.8.2output driving current . . . . .......................................... 119 14.9 control pin characteristics . . . . . ................................. 121 14.9.1asynchronous reset pin . . . . . . . . . . . . . . . . . .......................... 121 14.9.2ispsel pin ...................................................... 123 14.10 timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 124 14.10.1watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 124 14.10.216-bit timer . . . . . . . . . . . . . . . . . . . . . ................................ 124 14.11 communication interface characteristics . . . . . ................... 125 14.11.1spi - serial peripheral interface . . . . . . . . . . . . .......................... 125 14.11.2i2c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......... 127 14.12 8-bit adc characteristics . . . . . . . . ................................. 128 15 package characteristics . . . . . . ........................................ 130 15.1 package mechanical data . . . . . . . . . . . . ............................. 130 15.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . ................... 131 15.3 soldering and glueability information . . . . . . . . . . . . . . . . . . . . . ....... 132 16 device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . 133 16.1 option bytes . . . ................................. .................. 133 16.2 device ordering information and transfer of customer code . . . . 134 16.3 development tools . . . . . . . . . . . . . . . . . . . . . .......................... 136 16.3.1package/socket footprint proposal . . . . . ..................... 137 16.4 st7 application notes . . . . . . . . . . . . ................................. 138 16.5 to get more information . . . ....................................... 138 17 summary of changes . .................................................. 139 st72104g, st72215g, st72216g, st72254g 6/140 1 introduction the st72104g, st72215g, st72216g and st72254g devices are members of the st7 mi- crocontroller family. they can be grouped as fol- lows: st72254g devices are designed for mid-range applications with adc and i c interface capabili- ties. st72215/6g devices target the same range of applications but without i c interface. st72104g devices are for applications that do not need adc and i c peripherals. all devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set. the st72c104g, st72c215g, st72c216g and ST72C254G versions feature single-voltage flash memory with byte-by-byte in-situ pro- gramming (isp) capability. under software control, all devices can be placed in wait, slow, or halt mode, reducing power consumption when the application is in idle or stand-by state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. for easy reference, all parametric data are located in section 14 on page 96. figure 1. general block diagram 8-bit core alu address and data bus osc1 osc2 reset port b 16-bit timer a port a spi port c 8-bit adc watchdog pb7:0 (8 bits) pc5:0 (6 bits) multi osc internal clock control ram (256 bytes) pa7:0 (8 bits) v ss v dd power supply 16-bit timer b program (4 or 8k bytes) lvd + clock filter i 2 c memory 4 st72104g, st72215g, st72216g, st72254g 7/140 2 pin description figure 2. 28-pin so package pinout figure 3. 32-pin sdip package pinout 15 16 17 18 19 20 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 reset osc1 ain3/icap2_b/pc3 ain4/ocmp2_b/pc4 ain5/extclk_a/pc5 icap1_a/pb0 ocmp1_a/pb1 icap2_a/pb2 ocmp2_a/pb3 mosi/pb4 ispdata/miso/pb5 ispclk/sck/pb6 ss/pb7 osc2 v dd v ss pc2/mco/ain2 pc1/ocmp1_b/ain1 pc0/icap1_b/ain0 pa7 (hs) pa6 (hs)/sdai pa5 (hs) pa4 (hs)/scli pa3 (hs) pa2 (hs) pa1 (hs) pa0 (hs) ispsel ei1 ei0 ei0 or ei1 (hs) 20ma high sink capability eix associated external interrupt vector 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 29 30 31 32 reset osc1 ain3/icap2_b/pc3 ain4/ocmp2_b/pc4 ain5/extclk_a/pc5 icap1_a/pb0 ocmp1_a/pb1 icap2_a/pb2 ocmp2_a/pb3 mosi/pb4 ispdata/miso/pb5 ispclk/sck/pb6 ss/pb7 osc2 nc nc v dd v ss pc2/mco/ain2 pc1/ocmp1_b/ain1 pc0/icap1_b/ain0 pa7 (hs) pa6 (hs)/sdai pa5 (hs) pa4 (hs)/scli pa3 (hs) pa2 (hs) pa1 (hs) pa0 (hs) ispsel nc nc ei1 ei0 ei0 ei1 ei0 or ei1 (hs) 20ma high sink capability eix associated external interrupt vector 5 st72104g, st72215g, st72216g, st72254g 8/140 pin description (cont'd) for external pin connection guidelines, refer to section 14 oelectrical characteristicso on page 96. legend / abbreviations for table 1 : type: i = input, o = output, s = supply input level: a = dedicated analog input in/output level: c = cmos 0.3v dd /0.7v dd , c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = 20ma high sink (on n-buffer only) port and control configuration: input: float = floating, wpu = weak pull-up, int = interrupt 1) , ana = analog output: od = open drain 2) , pp = push-pull refer to section 10 oi/o portso on page 30 for more details on the software configuration of the i/o ports. the reset configuration of each pin is shown in bold. this configuration is valid as long as the device is in reset state. table 1. device pin description pin n pin name type level port / control main function (after reset) alternate function sdip32 so28 input output input output float wpu int ana od pp 1 1 reset i/o c t x x top priority non maskable interrupt (active low) 2 2 osc1 3) i external clock input or resonator oscillator in- verter input or resistor input for rc oscillator 3 3 osc2 3) o resonator oscillator inverter output or capaci- tor input for rc oscillator 4 4 pb7/ss i/o c t x ei1 x x port b7 spi slave select (active low) 5 5 pb6/sck/ispclk i/o c t x ei1 x x port b6 spi serial clock or isp clock 6 6 pb5/miso/ispdata i/o c t x ei1 x x port b5 spi master in/ slave out data or isp data 7 7 pb4/mosi i/o c t x ei1 x x port b4 spi master out / slave in data 8nc not connected 9nc 10 8 pb3/ocmp2_a i/o c t x ei1 x x port b3 timer a output compare 2 11 9 pb2/icap2_a i/o c t x ei1 x x port b2 timer a input capture 2 12 10 pb1 /ocmp1_a i/o c t x ei1 x x port b1 timer a output compare 1 13 11 pb0 /icap1_a i/o c t x ei1 x x port b0 timer a input capture 1 14 12 pc5/extclk_a/ain5 i/o c t x ei0/ei1 x x port c5 timer a input clock or adc analog input 5 15 13 pc4/ocmp2_b/ain4 i/o c t x ei0/ei1 x x port c4 timer b output compare 2 or adc analog input 4 16 14 pc3/ icap2_b/ain3 i/o c t x ei0/ei1 x x x port c3 timer b input capture 2 or adc analog input 3 6 st72104g, st72215g, st72216g, st72254g 9/140 notes : 1. in the interrupt input column, aeixo defines the associated external interrupt vector. if the weak pull-up column (wpu) is merged with the interrupt column (int), then the i/o configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. in the open drain output column, ato defines a true open drain i/o (p-buffer and protection diode to v dd are not implemented). see section 10 oi/o portso on page 30 and section 14.8 oi/o port pin char- acteristicso on page 118 for more details. 3. osc1 and osc2 pins connect a crystal or ceramic resonator, an external rc, or an external source to the on-chip oscillator see section 2 opin descriptiono on page 7 and section 14.5 oclock and tim- ing characteristicso on page 105 for more details. 17 15 pc2/mco/ain2 i/o c t x ei0/ei1 x x x port c2 main clock output (f cpu )or adc analog input 2 18 16 pc1/ocmp1_b/ain1 i/o c t x ei0/ei1 x x x port c1 timer b output compare 1 or adc analog input 1 19 17 pc0/icap1_b/ain0 i/o c t x ei0/ei1 x x x port c0 timer b input capture 1 or adc analog input 0 20 18 pa7 i/o c t hs x ei0 x x port a7 21 19 pa6 /sdai i/o c t hs x ei0 t port a6 i 2 c data 22 20 pa5 i/o c t hs x ei0 x x port a5 23 21 pa4 /scli i/o c t hs x ei0 t port a4 i 2 c clock 24 nc not connected 25 nc 26 22 pa3 i/o c t hs x ei0 x x port a3 27 23 pa2 i/o c t hs x ei0 x x port a2 28 24 pa1 i/o c t hs x ei0 x x port a1 29 25 pa0 i/o c t hs x ei0 x x port a0 30 26 ispsel i c x in situ programming selection (should be tied low in standard user mode). 31 27 v ss s ground 32 28 v dd s main power supply pin n pin name type level port / control main function (after reset) alternate function sdip32 so28 input output input output float wpu int ana od pp st72104g, st72215g, st72216g, st72254g 10/140 3 register & memory map as shown in the figure 4, the mcu is capable of addressing 64k bytes of memories and i/o regis- ters. the available memory locations consist of 128 bytes of register location, 256 bytes of ram and up to 8kbytes of user program memory. the ram space includes up to 128 bytes for the stack from 0100h to 017fh. the highest address bytes contain the user reset and interrupt vectors. important: memory locations marked as are- servedo must never be accessed. accessing a re- served area can have unpredictable effects on the device. figure 4. memory map 0000h program memory (4k, 8 kbytes) interrupt & reset vectors hw registers dfffh 0080h 007fh (see table 2) e000h ffdfh ffe 0h fff fh (see table 5 on page 26) 0180h reserved 017fh short addressing ram 0100h 017fh 0080h 00ffh 256 bytes ram 4 kbytes f000h e000h 8 kbytes ffff h zero page (128 bytes) stack or 16-bit addressing ram (128 bytes) st72104g, st72215g, st72216g, st72254g 11/140 table 2. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port c pcdr pcddr pcor port c data register port c data direction register port c option register 00h 1) 00h 00h r/w 2) r/w 2) r/w 2) 0003h reserved (1 byte) 0004h 0005h 0006h port b pbdr pbddr pbor port b data register port b data direction register port b option register 00h 1) 00h 00h r/w r/w r/w. 0007h reserved (1 byte) 0008h 0009h 000ah port a padr paddr paor port a data register port a data direction register port a option register 00h 1) 00h 00h r/w r/w r/w 000bh to 001fh reserved (21 bytes) 0020h miscr1 miscellaneous register 1 00h r/w 0021h 0022h 0023h spi spidr spicr spisr spi data i/o register spi control register spi status register xxh 0xh 00h r/w r/w read only 0024h watchdog wdgcr watchdog control register 7fh r/w 0025h crsr clock, reset, supply control / status register 000x 000x r/w 0026h 0027h reserved (2 bytes) 0028h 0029h 002ah 002bh 002ch 002dh 002eh i 2 c i2ccr i2csr1 i2csr2 i2cccr i2coar1 i2coar2 i2cdr control register status register 1 status register 2 clock control register own address register 1 own address register 2 data register 00h 00h 00h 00h 00h 00h 00h r/w read only read only r/w r/w r/w r/w 002fh to 0030h reserved (4 bytes) st72104g, st72215g, st72216g, st72254g 12/140 legend : x=undefined, r/w=read/write notes : 1. the contents of the i/o port dr registers are readable only in output configuration. in input configura- tion, the values of the i/o pins are returned instead of the dr register contents. 2. the bits associated with unavailable pins must always keep their reset value. 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a tacr2 tacr1 tasr taic1hr taic1lr taoc1hr taoc1lr tachr taclr taachr taaclr taic2hr taic2lr taoc2hr taoc2lr timer a control register 2 timer a control register 1 timer a status register timer a input capture 1 high register timer a input capture 1 low register timer a output compare 1 high register timer a output compare 1 low register timer a counter high register timer a counter low register timer a alternate counter high register timer a alternate counter low register timer a input capture 2 high register timer a input capture 2 low register timer a output compare 2 high register timer a output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0040h miscr2 miscellaneous register 2 00h r/w 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b tbcr2 tbcr1 tbsr tbic1hr tbic1lr tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic2hr tbic2lr tboc2hr tboc2lr timer b control register 2 timer b control register 1 timer b status register timer b input capture 1 high register timer b input capture 1 low register timer b output compare 1 high register timer b output compare 1 low register timer b counter high register timer b counter low register timer b alternate counter high register timer b alternate counter low register timer b input capture 2 high register timer b input capture 2 low register timer b output compare 2 high register timer b output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h to 006fh reserved (32 bytes) 0070h 0071h adc adcdr adccsr data register control/status register 00h 00h read only r/w 0072h to 007fh reserved (14 bytes) address block register label register name reset status remarks st72104g, st72215g, st72216g, st72254g 13/140 4 flash program memory 4.1 introduction flash devices have a single voltage non-volatile flash memory that may be programmed in-situ (or plugged in a programming tool) on a byte-by- byte basis. 4.2 main features n remote in-situ programming (isp) mode n up to 16 bytes programmed in the same cycle n mtp memory (multiple time programmable) n read-out memory protection against piracy 4.3 structural organisation the flash program memory is organised in a single 8-bit wide memory block which can be used for storing both code and data constants. the flash program memory is mapped in the up- per part of the st7 addressing space and includes the reset and interrupt user vector area . 4.4 in-situ programming (isp) mode the flash program memory can be programmed using remote isp mode. this isp mode allows the contents of the st7 program memory to be up- dated using a standard st7 programming tools af- ter the device is mounted on the application board. this feature can be implemented with a minimum number of added components and board area im- pact. an example remote isp hardware interface to the standard st7 programming tool is described be- low. for more details on isp programming, refer to the st7 programming specification. remote isp overview the remote isp mode is initiated by a specific se- quence on the dedicated ispsel pin. the remote isp is performed in three steps: selection of the ram execution mode download of remote isp code in ram execution of remote isp code in ram to pro- gram the user program into the flash remote isp hardware configuration in remote isp mode, the st7 has to be supplied with power (v dd and v ss ) and a clock signal (os- cillator and application crystal circuit for example). this mode needs five signals (plus the v dd signal if necessary) to be connected to the programming tool. this signals are: reset: device reset v ss : device ground power supply ispclk: isp output serial clock pin ispdata: isp input serial data pin ispsel: remote isp mode selection. this pin must be connected to v ss on the application board through a pull-down resistor. if any of these pins are used for other purposes on the application, a serial resistor has to be imple- mented to avoid a conflict if the other device forces the signal level. figure 5 shows a typical hardware interface to a standard st7 programming tool. for more details on the pin locations, refer to the device pinout de- scription. figure 5. typical remote isp interface 4.5 memory read-out protection the read-out protection is enabled through an op- tion bit. for flash devices, when this option is selected, the program and data stored in the flash memo- ry are protected against read-out piracy (including a re-write protection). when this protection option is removed the entire flash program memory is first automatically erased. however, the e 2 prom data memory (when available) can be protected only with rom devices. ispsel v ss reset ispclk ispdata osc1 osc2 v dd st7 he10 connector type to programming tool 10k w c l0 c l1 application 47k w 1 xtal st72104g, st72215g, st72216g, st72254g 14/140 5 central processing unit 5.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 main features n 63 basic instructions n fast 8-bit by 8-bit multiply n 17 main addressing modes n two 8-bit index registers n 16-bit stack pointer n low power modes n maskable hardware interrupts n non-maskable software interrupt 5.3 cpu registers the 6 cpu registers shown in figure 1 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede in- struction (pre) to indicate that the following in- struction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 6. cpu registers accumulator x index register y index register stack pointer conditio n code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 87 0 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value st72104g, st72215g, st72216g, st72254g 15/140 cpu registers (cont'd) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 3 = i interrupt mask . this bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret in- structions and is tested by the jrm and jrnm in- structions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptable because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the abit test and brancho, shift and rotate instructions. 70 111hinzc st72104g, st72215g, st72216g, st72254g 16/140 6 central processing unit (cont'd) stack pointer (sp) read/write reset value: 01 7fh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 7). since the stack is 128 bytes deep, the 9 most sig- nificant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp6 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 7. when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. figure 7. stack manipulation example 15 8 00000001 70 0 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 017fh @ 0100h stack higher address = 017fh stack lower address = 0100h st72104g, st72215g, st72216g, st72254g 17/140 7 supply, reset and clock management the st72104g, st72215g, st72216g and st72254g microcontrollers include a range of util- ity features for securing the application in critical situations (for example in case of a power brown- out), and reducing the number of external compo- nents. an overview is shown in figure 8. see section 14 oelectrical characteris- ticso on page 96 for more details. main features n supply manager with main supply low voltage detection (lvd) n reset sequence manager (rsm) n multi-oscillator (mo) 4 crystal/ceramic resonator oscillators 1 external rc oscillator 1 internal rc oscillator n clock security system (css) clock filter backup safe oscillator figure 8. clock, reset and supply block diagram ie d 0 0 0 0 rf rf crsr css wdg f osc css inter rupt lvd low voltage detecto r (lvd) multi- oscillator (mo) from watch dog perip heral osc1 reset vdd vss reset sequen ce manager (rsm) clock filter safe osc clock secur ity syste m (css) main clock controller (mcc) mco f cpu osc2 st72104g, st72215g, st72216g, st72254g 18/140 7.1 low voltage detector (lvd) to allow the integration of power management features in the application, the low voltage detec- tor function (lvd) generates a static reset when the v dd supply voltage is below a v it- reference value. this means that it secures the power-up as well as the power-down keeping the st7 in reset. the v it- reference value for a voltage drop is lower than the v it+ reference value for power-on in order to avoid a parasitic reset when the mcu starts run- ning and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: v it+ when v dd is rising v it- when v dd is falling the lvd function is illustrated in the figure 9. provided the minimum v dd value (guaranteed for the oscillator frequency) is above v it- , the mcu can only be in two modes: under full software control in static safe reset in these conditions, secure operation is always en- sured for the application without the need for ex- ternal reset hardware. during a low voltage detector reset, the reset pin is held low, thus permitting the mcu to reset other devices. notes : 1. the lvd allows the device to be used without any external reset circuitry. 2. three different reference levels are selectable through the option byte according to the applica- tion requirement. lvd application note application software can detect a reset caused by the lvd by reading the lvdrf bit in the crsr register. this bit is set by hardware when a lvd reset is generated and cleared by software (writing zero). figure 9. low voltage detector vs reset v dd v it+ reset v it- v hyst st72104g, st72215g, st72216g, st72254g 19/140 7.2 reset sequence manager (rsm) 7.2.1 introduction the reset sequence manager includes three re- set sources as shown in figure 11: n external reset source pulse n internal lvd reset (low voltage detection) n internal watchdog reset these sources act on the reset pin and it is al- ways kept low during the delay phase. the reset service routine vector is fixed at ad- dresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 10: n delay depending on the reset source n 4096 cpu clock cycle delay n reset vector fetch the 4096 cpu clock cycle delay allows the oscil- lator to stabilise and ensures that recovery has taken place from the reset state. the reset vector fetch phase duration is 2 clock cycles. figure 10. reset sequence phases figure 11. reset block diagram reset delay internal reset 4096 clock cycles fetch vector f cpu counter reset r on v dd watchdog reset lvd reset internal reset st72104g, st72215g, st72216g, st72254g 20/140 reset sequence manager (cont'd) 7.2.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in ac- cordance with the input voltage. it can be pulled low by external circuitry to reset the device. see electrical characteristics section for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized. this detection is asynchro- nous and therefore the mcu can enter reset state even in halt mode. the reset pin is an asynchronous signal which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris- tics section. two reset sequences can be associated with this reset source: short or long external reset pulse (see figure 12). starting from the external reset pulse recogni- tion, the device reset pin acts as an output that is pulled low during at least t w(rstl)out . 7.2.3 internal low voltage detection reset two different reset sequences caused by the in- ternal lvd circuitry can be distinguished: n power-on reset n voltage drop reset the device reset pin acts as an output that is pulled low when v dd st72104g, st72215g, st72216g, st72254g 22/140 7.4 clock security system (css) the clock security system (css) protects the st7 against main clock problems. to allow the in- tegration of the security features in the applica- tions, it is based on a clock filter control and an in- ternal safe oscillator. the css can be enabled or disabled by option byte. 7.4.1 clock filter control the clock filter is based on a clock frequency limi- tation function. this filter function is able to detect and filter high frequency spikes on the st7 main clock. if the oscillator is not working properly (e.g. work- ing at a harmonic frequency of the resonator), the current active oscillator clock can be totally fil- tered, and then no clock signal is available for the st7 from this oscillator anymore. if the original clock source recovers, the filtering is stopped au- tomatically and the oscillator supplies the st7 clock. 7.4.2 safe oscillator control the safe oscillator of the css block is a low fre- quency back-up clock source (see figure 13). if the clock signal disappears (due to a broken or disconnected resonator...) during a safe oscillator period, the safe oscillator delivers a low frequency clock signal which allows the st7 to perform some rescue operations. automatically, the st7 clock source switches back from the safe oscillator if the original clock source recovers. limitation detection the automatic safe oscillator selection is notified by hardware setting the cssd bit of the crsr register. an interrupt can be generated if the cs- sie bit has been previously set. these two bits are described in the crsr register description. 7.4.3 low power modes 7.4.4 interrupts the css interrupt event generates an interrupt if the corresponding enable control bit (cssie) is set and the interrupt mask in the cc register is re- set (rim instruction). note 1: this interrupt allows to exit from active-halt mode if this mode is available in the mcu. figure 13. clock filter function and safe oscillator function mode description wait no effect on css. css interrupt cause the device to exit from wait mode. halt the crsr register is frozen. the css (in- cluding the safe oscillator) is disabled until halt mode is exited. the previous css configuration resumes when the mcu is woken up by an interrupt with aexit from halt modeo capability or from the counter reset value when the mcu is woken up by a reset. interrupt event event flag enable control bit exit from wait exit from halt 1) css event detection (safe oscillator acti- vated as main clock) cssd cssie yes no f osc /2 f cpu f osc /2 f cpu f sfosc safe oscillator function clock filter function st72104g, st72215g, st72216g, st72254g 23/140 7.5 clock reset and supply register description (crsr) read/write reset value: 000x 000x (xxh) bit 7:5 = reserved , always read as 0. bit 4 = lvdrf lvd reset flag this bit indicates that the last reset was gener- ated by the lvd block. it is set by hardware (lvd reset) and cleared by software (writing zero). see wdgrf flag description for more details. when the lvd is disabled by option byte, the lvdrf bit value is undefined. bit 3 = reserved , always read as 0. bit 2 = cssie clock security syst . interrupt enable this bit enables the interrupt when a disturbance is detected by the clock security system (cssd bit set). it is set and cleared by software. 0: clock security system interrupt disabled 1: clock security system interrupt enabled refer to table 5, ainterrupt mapping,o on page 26 for more details on the css interrupt vector. when the css is disabled by option byte, the cssie bit has no effect. bit 1 = cssd clock security system detection this bit indicates that the safe oscillator of the clock security system block has been selected by hardware due to a disturbance on the main clock signal (f osc ). it is set by hardware and cleared by reading the crsr register when the original oscil- lator recovers. 0: safe oscillator is not active 1: safe oscillator has been activated when the css is disabled by option byte, the cssd bit value is forced to 0. bit 0 = wdgrf watchdog reset flag this bit indicates that the last reset was gener- ated by the watchdog peripheral. it is set by hard- ware (watchdog reset) and cleared by software (writing zero) or an lvd reset (to ensure a sta- ble cleared state of the wdgrf flag when the cpu starts). combined with the lvdrf flag information, the flag description is given by the following table. application notes the lvdrf flag is not cleared when another re- set type occurs (external or watchdog), the lvdrf flag remains set to keep trace of the origi- nal failure. in this case, a watchdog reset can be detected by software while an external reset can not. table 4. clock, reset and supply register map and reset values 70 000 lvd rf 0 css ie css d wdg rf reset sources lvdrf wdgrf external reset pin 0 0 watchdog 0 1 lvd 1 x address (hex.) register label 76543210 0025h crsr reset value 0 0 0 lvdrf x0 cssie 0 cssd 0 wdgrf x st72104g, st72215g, st72216g, st72254g 24/140 7.6 main clock controller (mcc) the main clock controller (mcc) supplies the clock for the st7 cpu and its internal peripherals. it allows slow power saving mode to be man- aged by the application. all functions are managed by the miscellaneous register 1 (miscr1). the mcc block consists of: n a programmable cpu clock prescaler n a clock-out signal to supply external devices the prescaler allows the selection of the main clock frequency and is controlled by three bits of the miscr1: cp1, cp0 and sms. the clock-out capability consists of a dedicated i/o port pin configurable as an f cpu clock output to drive external devices. it is controlled by the mco bit in the miscr1 register. see section 11 omiscellaneous regis- terso on page 36 for more details. figure 14. main clock controller (mcc) block diagram div2,4,8,16 div 2 sms cp1 cp0 cpu clock miscr1 clock to can to cpu and peripherals f osc f cpu mco port function alternate mco - - - - f osc /2 peripheral st72104g, st72215g, st72216g, st72254g 25/140 8 interrupts the st7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the interrupt mapping table and a non- maskable software interrupt (trap). the interrupt processing flowchart is shown in figure 1. the maskable interrupts must be enabled clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsec- tion). when an interrupt has to be serviced: normal processing is suspended at the end of the current instruction execution. the pc, x, a and cc registers are saved onto the stack. the i bit of the cc register is set to prevent addi- tional interrupts. the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the interrupt mapping table for vector address- es). the interrupt service routine should finish with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit will be cleared and the main program will resume. priority management by default, a servicing interrupt cannot be inter- rupted because the i bit is set by hardware enter- ing in interrupt routine. in the case when several interrupts are simultane- ously pending, an hardware priority defines which one will be serviced first (see the interrupt map- ping table). interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specifi- cally mentioned interrupts allow the processor to leave the halt low power mode (refer to the aexit from halta column in the interrupt mapping ta- ble). 8.1 non maskable software interrupt this interrupt is entered when the trap instruc- tion is executed regardless of the state of the i bit. it will be serviced according to the flowchart on figure 1. 8.2 external interrupts external interrupt vectors can be loaded into the pc register if the corresponding external interrupt occurred and if the i bit is cleared. these interrupts allow the processor to leave the halt low power mode. the external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). an external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins, connected to the same inter- rupt vector, are configured as interrupts, their sig- nals are logically anded before entering the edge/ level detection block. caution: the type of sensitivity defined in the mis- cellaneous or interrupt register (if available) ap- plies to the ei source. in case of an anded source (as described on the i/o ports section), a low level on an i/o pin configured as input with interrupt, masks the interrupt request even in case of rising- edge sensitivity. 8.3 peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: the i bit of the cc register is cleared. the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by: writing a0o to the corresponding bit in the status register or access to the status register while the flag is set followed by a read or write of an associated reg- ister. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being en- abled) will therefore be lost if the clear sequence is executed. st72104g, st72215g, st72216g, st72254g 26/140 interrupts (cont'd) figure 15. interrupt processing flowchart table 5. interrupt mapping note 1. configurable by option byte. n source block description register label priority order exit from halt address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 ei0 external interrupt port a7..0 (c5..0 1 ) yes fffah-fffbh 1 ei1 external interrupt port b7..0 (c5..0 1 ) fff8h-fff9h 2 css clock security system interrupt crsr no fff6h-fff7h 3 spi spi peripheral interrupts spisr fff4h-fff5h 4 timer a timer a peripheral interrupts tasr fff2h-fff3h 5 not used fff0h-fff1h 6 timer b timer b peripheral interrupts tbsr no ffeeh-ffe fh 7 not used ffech-ffedh 8 not used ffeah-ffebh 9 not used ffe8h-ffe9h 10 not used ffe6h-ffe7h 11 i c i c peripheral interrupt i2csrx no ffe4h-ffe5h 12 not used ffe2h-ffe3h 13 not used ffe0h-ffe1h i bit set? y n iret? y n from reset load pc from interrupt vecto r stack pc, x, a, cc set i bit fetch next instr uction execu te instruction this clears i bit by default restore pc, x, a, cc from stack inte rrupt y n pending ? st72104g, st72215g, st72216g, st72254g 27/140 9 power saving modes 9.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, three main power saving modes are implemented in the st7 (see figure 16). after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f cpu ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instruction whose action depends on the oscillator status. figure 16. power saving mode transitions 9.2 slow mode this mode has two targets: to reduce power consumption by decreasing the internal clock in the device, to adapt the internal clock frequency (f cpu )to the available supply voltage. slow mode is controlled by three bits in the miscr1 register: the sms bit which enables or disables slow mode and two cpx bits which select the internal slow frequency (f cpu ). in this mode, the oscillator frequency can be divid- ed by 4, 8, 16 or 32 instead of 2 in normal operat- ing mode. the cpu and peripherals are clocked at this lower frequency. note : slow-wait mode is activated when enter- ing wait mode while the device is already in slow mode. figure 17. slow mode clock transitions power consumption wait slow run halt high low slow wait 00 01 sms cp1:0 f cpu new slow normal run mode miscr1 frequ ency request request f osc /2 f osc /4 f osc /8 f osc /2 st72104g, st72215g, st72216g, st72254g 28/140 power saving modes (cont'd) 9.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the awfio st7 software instruction. all peripherals remain active. during wait mode, the i bit of the cc register is forced to 0, to enable all interrupts. all other registers and memory re- main unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereup- on the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 18. figure 18. wait mode flow-chart note: 1. before servicing an interrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. wfi instruction reset interrupt y n n y cpu oscillator peripherals ibit on on 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off 1 on cpu oscillator peripherals i bit on on x 1) on 4096 cpu clock cycle delay st72104g, st72215g, st72216g, st72254g 29/140 power saving modes (cont'd) 9.4 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the st7 halt instruction (see figure 20). the mcu can exit halt mode on reception of ei- ther a specific interrupt (see table 5, ainterrupt mapping,o on page 26) or a reset. when exiting halt mode by means of a reset or an interrupt, the oscillator is immediately turned on and the 4096 cpu cycle delay is used to stabilize the os- cillator. after the start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 19). when entering halt mode, the i bit in the cc reg- ister is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes immedi- ately. in the halt mode the main oscillator is turned off causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla- tor). the compatibility of watchdog operation with halt mode is configured by the awdghalto op- tion bit of the option byte. the halt instruction when executed while the watchdog system is en- abled, can generate a watchdog reset (see section 16.1 ooption byteso on page 133 for more details). figure 19. halt mode timing overview figure 20. halt mode flow-chart notes: 1. wdghalt is an option bit. see option byte sec- tion for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). re- fer to table 5, ainterrupt mapping,o on page 26 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. halt run run 4096 cpu cycle delay reset or interrupt halt instruction fetch vector halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) ibit off off 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off 1 on cpu oscillator peripherals ibit on on x 4) on 4096 cpu clock cycle delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 st72104g, st72215g, st72216g, st72254g 30/140 10 i/o ports 10.1 introduction the i/o ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip pe- ripherals. an i/o port contains up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 10.2 functional description each port has 2 main registers: data register (dr) data direction register (ddr) and one optional register: option register (or) each i/o pin may be programmed using the corre- sponding register bits in the ddr and or regis- ters: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not pro- vide this register refer to the i/o port implementa- tion section). the generic i/o block diagram is shown in figure 21 10.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. notes : 1. writing the dr register modifies the latch value but does not affect the pin status. 2. when switching from input to output mode, the dr register has to be written first to drive the cor- rect level on the pin as soon as the port is config- ured as an output. external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external inter- rupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the mis- cellaneous register. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see pinout description and interrupt section). if several input pins are se- lected simultaneously as interrupt source, these are logically anded. for this reason if one of the interrupt pins is tied low, it masks the other ones. in case of a floating input with interrupt configura- tion, special care must be taken when changing the configuration (see figure 22). the external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. to clear an unwanted pending interrupt by software, the sensitivity bits in the miscellane- ous register must be modified. 10.2.2 output modes the output configuration is selected by setting the corresponding ddr register bit. in this case, writ- ing the dr register applies this digital value to the i/o pin through the latch. then reading the dr reg- ister returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. dr register value and output pin status: 10.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over the standard i/o programming. when the signal is coming from an on-chip periph- eral, the i/o pin is automatically configured in out- put mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin must be configured in input mode. in this case, the pin state is also digitally readable by addressing the dr register. note : input pull-up configuration can cause unex- pected value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as in- put and output, this pin has to be configured in in- put floating mode. dr push-pu ll open-drain 0v ss vss 1v dd floating st72104g, st72215g, st72216g, st72254g 31/140 i/o ports (cont'd) figure 21. i/o port general block diagram table 6. i/o port mode options legend : ni - not implemented off - implemented not activated on - implemented and activated note : the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ss is implemented to protect the de- vice against positive stress. configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (see note) dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up configuration p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external source (ei x ) interrupt polarity selection cmos schmitt trigger register access st72104g, st72215g, st72216g, st72254g 32/140 i/o ports (cont'd) table 7. i/o port configurations notes: 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read the alternate function output status. 2. when the i/o port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the dr register content. hardware configu ration input 1) open-drain output 2) push-pull output 2) configuration pad v dd r pu external interru pt polarity data bus pull-up interrupt dr register access w r from other pins source (ei x ) selection dr register config uration alternate input not implemented in true open drain i/o ports analog input pad r pu data b us dr dr regist er access r/w v dd alternate alternate enable output regist er not implemented in true open drain i/o ports pad r pu data b us dr dr regist er access r/w v dd alternate alternate enable output regist er not implemented in true open drain i/o ports st72104g, st72215g, st72216g, st72254g 33/140 i/o ports (cont'd) caution : the alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the select- ed pin to the common analog rail which is connect- ed to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning : the analog input voltage level must be within the limits stated in the absolute maxi- mum ratings. 10.3 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr and or registers and specific feature of the i/o port such as adc in- put or true open drain. switching these i/o ports from one state to anoth- er should be done in a sequence that prevents un- wanted side effects. recommended safe transi- tions are illustrated in figure 22 other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 22. interrupt i/o port state transitions the i/o port register configurations are summa- rized as follows. interrupt ports pa7, pa5, pa3:0, pb7:0, pc5:0 (with pull-up) true open drain interrupt ports pa6, pa4 (without pull-up) table 8. port configuration mode ddr or floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 floating interrupt input 0 1 open drain (high sink ports) 1 x 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or port pin name inpu t (ddr = 0) output (ddr = 1) or = 0 or = 1 or = 0 or = 1 high-sink port a pa7 floating pull-up interrupt open drain push-pull yes pa6 floating floating interrupt true open-drain pa5 floating pull-up interrupt open drain push-pull pa4 floating floating interrupt true open-drain pa3:0 floating pull-up interrupt open drain push-pull port b pb7:0 floating pull-up interrupt open drain push-pull no port c pc7:0 floating pull-up interrupt open drain push-pull st72104g, st72215g, st72216g, st72254g 34/140 i/o ports (cont'd) 10.4 low power modes 10.5 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and the i-bit in the cc reg- ister is reset (rim instruction). 10.6 register description data register (dr) port x data register pxdr with x = a, b or c. read/write reset value: 0000 0000 (00h) bit 7:0 = d[7:0] data register 8 bits. the dr register has a specific behaviour accord- ing to the selected input/output configuration. writ- ing the dr register is always taken into account even if the pin is configured as an input; this allows always having the expected level on the pin when toggling to output mode. reading the dr register returns either the dr register latch content (pin configured as output) or the digital value applied to the i/o pin (pin configured as input). data direction register (ddr) port x data direction register pxddr with x = a, b or c. read/write reset value: 0000 0000 (00h) bit 7:0 = dd[7:0] data direction register 8 bits. the ddr register gives the input/output direction configuration of the pins. each bit is set and cleared by software. 0: input mode 1: output mode option register (or) port x option register pxor with x = a, b or c. read/write reset value: 0000 0000 (00h) bit 7:0 = o[7:0] option register 8 bits. for specific i/o pins, this register is not implement- ed. in this case the ddr register is enough to se- lect the i/o pin configuration. the or register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. each bit is set and cleared by software. input mode: 0: floating input 1: pull-up input with or without interrupt output mode: 0: output open drain (with p-buffer deactivated) 1: output push-pull (when available) mode description wait no effect on i/o ports. external interrupts cause the device to exit from wait mode. halt no effect on i/o ports. external interrupts cause the device to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx orx yes yes 70 d7 d6 d5 d4 d3 d2 d1 d0 70 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 70 o7 o6 o5 o4 o3 o2 o1 o0 st72104g, st72215g, st72216g, st72254g 35/140 i/o ports (cont'd) table 9. i/o port register map and reset values address (hex.) register label 76543210 reset value of all i/o port registers 00000000 0000h pcdr msb lsb 0001h pcddr 0002h pcor 0004h pbdr msb lsb 0005h pbddr 0006h pbor 0008h padr msb lsb 0009h paddr 000ah paor st72104g, st72215g, st72216g, st72254g 36/140 11 miscellaneous registers the miscellaneous registers allow control over several different features such as the external in- terrupts or the i/o alternate functions. 11.1 i/o port interrupt sensitivity the external interrupt sensitivity is controlled by the isxx bits of the miscellaneous register and the option byte. this control allows having two ful- ly independent external interrupt source sensitivi- ties with configurable sources (using extit option bit) as shown in figure 23 and figure 24. each external interrupt source can be generated on four different events on the pin: n falling edge n rising edge n falling and rising edge n falling edge and low level to guarantee correct functionality, the sensitivity bits in the miscr1 register must be modified only when the i bit of the cc register is set to 1 (inter- rupt masked). see i/o port register and miscella- neous register descriptions for more details on the programming. 11.2 i/o port alternate functions the miscr registers manage four i/o port miscel- laneous alternate functions: n main clock signal (f cpu ) output on pc2 n spi pin configuration: ss pin internal control to use the pb7 i/o port function while the spi is active. master output capability on mosi pin (pb4) deactivated while the spi is active. slave output capability on miso pin (pb5) de- activated while the spi is active. these functions are described in detail in the sec- tion 11.3 omiscellaneous register de- scriptiono on page 37. figure 23. ext. interrupt sensitivity (extit=0) figure 24. ext. interrupt sensitivity (extit=1) ei0 interr upt source is00 is01 miscr1 sensiti vity control pa7 pa0 pc5 pc0 pb7 pb0 is10 is11 miscr1 sensiti vity control ei1 interr upt source pa7 pa0 is00 is01 miscr1 sensi tivity control ei0 inter rupt source ei1 inter rupt source is10 is11 miscr1 sensi tivity control pb7 pb0 pc5 pc0 st72104g, st72215g, st72216g, st72254g 37/140 miscellaneous registers (cont'd) 11.3 miscellaneous register description miscellaneous register 1 (miscr1) read/write reset value: 0000 0000 (00h) bit 7:6 = is1[1:0] ei1 sensitivity the interrupt sensitivity, defined using the is1[1:0] bits, is applied to the ei1 external interrupts. these two bits can be written only when the i bit of the cc register is set to 1 (interrupt masked). ei1: port b (c optional) bit 5 = mco main clock out selection this bit enables the mco alternate function on the pc2 i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f cpu on i/o port) bit 4:3 = is0[1:0] ei0 sensitivity the interrupt sensitivity, defined using the is0[1:0] bits, is applied to the ei0 external interrupts. these two bits can be written only when the i bit of the cc register is set to 1 (interrupt masked). ei0: port a (c optional) bit 2:1 = cp[1:0] cpu clock prescaler these bits select the cpu clock prescaler which is applied in the different slow modes. their action is conditioned by the setting of the sms bit. these two bits are set and cleared by software bit 0 = sms slow mode select this bit is set and cleared by software. 0: normal mode. f cpu = f osc /2 1: slow mode. f cpu is given by cp1, cp0 see low power consumption mode and mcc chapters for more details. 70 is11 is10 mco is01 is00 cp1 cp0 sms external interrupt sensitivity is11 is10 falling edge & low level 0 0 rising edge only 0 1 falling edge only 1 0 rising and falling edge 1 1 external interrupt sensitivity is01 is00 falling edge & low level 0 0 rising edge only 0 1 falling edge only 1 0 rising and falling edge 1 1 f cpu in slow mode cp1 cp0 f osc /4 0 0 f osc /8 1 0 f osc /16 0 1 f osc /32 1 1 st72104g, st72215g, st72216g, st72254g 38/140 miscellaneous registers (cont'd) miscellaneous register 2 (miscr2) read/write reset value: 0000 0000 (00h) bit 7:4 = reserved always read as 0 bit 3 = mod spi master output disable this bit is set and cleared by software. when set, it disables the spi master (mosi) output signal. 0: spi master output enabled. 1: spi master output disabled. bit 2 = sod spi slave output disable this bit is set and cleared by software. when set it disable the spi slave (miso) output signal. 0: spi slave output enabled. 1: spi slave output disabled. bit 1 = ssm ss mode selection this bit is set and cleared by software. 0: normal mode - the level of the spi ss signal is input from the external ss pin. 1: i/o mode, the level of the spi ss signal is read from the ssi bit. bit 0 = ssi ss internal mode this bit replaces the ss pin of the spi when the ssm bit is set to 1. (see spi description). it is set and cleared by software. table 10. miscellaneous register map and reset values 70 0 0 0 0 mod sod ssm ssi address (hex.) register label 76543210 0020h miscr1 reset value is11 0 is10 0 mco 0 is01 0 is00 0 cp1 0 cp0 0 sms 0 0040h miscr2 reset value 0 0 0 0 mod 0 sod 0 ssm 0 ssi 0 st72104g, st72215g, st72216g, st72254g 39/140 12 on-chip peripherals 12.1 watchdog timer (wdg) 12.1.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counter's contents before the t6 bit be- comes cleared. 12.1.2 main features n programmable timer (64 increments of 12288 cpu cycles) n programmable reset n reset (if watchdog activated) when the t6 bit reaches zero n optional reset on halt instruction (configurable by option byte) n hardware watchdog selectable by option byte. 12.1.3 functional description the counter value stored in the cr register (bits t6:t0), is decremented every 12,288 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t6:t0) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. the application program must write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. the value to be stored in the cr register must be between ffh and c0h (see table 11 . watchdog timing (fcpu = 8 mhz)): the wdga bit is set (watchdog enabled) the t6 bit is set to prevent generating an imme- diate reset the t5:t0 bits contain the number of increments which represents the time delay before the watchdog produces a reset. figure 25. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) 12288 t1 t2 t3 t4 t5 st72104g, st72215g, st72216g, st72254g 40/140 watchdog timer (cont'd) table 11. watchdog timing (f cpu = 8 mhz) notes: following a reset, the watchdog is disa- bled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). 12.1.4 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the cr is not used. refer to the device-specific option byte descrip- tion. 12.1.5 low power modes wait instruction no effect on watchdog. halt instruction if the watchdog reset on halt option is selected by option byte, a halt instruction causes an im- mediate reset generation if the watchdog is acti- vated (wdga bit is set). 12.1.5.1 using halt mode with the wdg (option) if the watchdog reset on halt option is not se- lected by option byte, the halt mode can be used when the watchdog is enabled. in this case, the halt instruction stops the oscilla- tor. when the oscillator is stopped, the wdg stops counting and is no longer able to generate a reset until the microcontroller receives an external inter- rupt or a reset. if an external interrupt is received, the wdg re- starts counting after 4096 cpu clocks. if a reset is generated, the wdg is disabled (reset state). recommendations make sure that an external event is available to wake up the microcontroller from halt mode. before executing the halt instruction, refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcon- troller. when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as ainput pull-up with interrupto before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to ex- ternal interference or by an unforeseen logical condition. for the same reason, reinitialize the level sensi- tiveness of each external interrupt as a precau- tionary measure. the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo- ry. for example, avoid defining a constant in rom with the value 0x8e. as the halt instruction clears the i bit in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before execut- ing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 12.1.6 interrupts none. 12.1.7 register description control register (cr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled bit 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). cr register initial value wdg timeout period (ms) max ffh 98.304 min c0h 1.536 70 wdga t6 t5 t4 t3 t2 t1 t0 st72104g, st72215g, st72216g, st72254g 41/140 watchdog timer (cont'd) table 12. watchdog timer register map and reset values address (hex.) register label 76543210 0024h wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 st72104g, st72215g, st72216g, st72254g 42/140 12.2 16-bit timer 12.2.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including measuring the pulse lengths of up to two input sig- nals ( input capture ) or generating up to two output waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the cpu clock prescaler. some st7 devices have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are synchronized after a mcu reset as long as the timer clock frequen- cies are not modified. this description covers one or two 16-bit timers. in st7 devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 12.2.2 main features n programmable prescaler: f cpu divided by 2, 4 or 8. n overflow status flag and maskable interrupt n external clock input (must be at least 4 times slower than the cpu clock speed) with the choice of active edge n output compare functions with: 2 dedicated 16-bit registers 2 dedicated programmable signals 2 dedicated status flags 1 dedicated maskable interrupt n input capture functions with: 2 dedicated 16-bit registers 2 dedicated active edge selection signals 2 dedicated status flags 1 dedicated maskable interrupt n pulse width modulation mode (pwm) n one pulse mode n 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk)* the block diagram is shown in figure 26. *note: some timer pins may not be available (not bonded) in some st7 devices. refer to the device pin out description. when reading an input signal on a non-bonded pin, the value will always be `1'. 12.2.3 functional description 12.2.3.1 counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high & low. counter register (cr): counter high register (chr) is the most sig- nificant byte (ms byte). counter low register (clr) is the least sig- nificant byte (ls byte). alternate counter register (acr) alternate counter high register (achr) is the most significant byte (ms byte). alternate counter low register (aclr) is the least significant byte (ls byte). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register (sr). (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit tim- er). the reset value of both counters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bits of the cr2 register, as illustrated in table 13 clock control bits. the value in the counter register re- peats every 131.072, 262.144 or 524.288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency. st72104g, st72215g, st72216g, st72254g 43/140 16-bit timer (cont'd) figure 26. timer block diagram mcu-peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 0 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (status register) sr 6 16 888 8 88 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin pin register register note: if ic, oc and to interrupt requests have separate vectors then the last or is not present (see device interrupt vector table) (see note) st72104g, st72215g, st72216g, st72254g 44/140 16-bit timer (cont'd) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the ls byte of the count value at the time of the read. whatever the timer mode used (input capture, out- put compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: the tof bit of the sr register is set. a timer interrupt is generated if: toie bit of the cr1 register is set and i bit of the cc register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. note: the tof bit is not cleared by accessing the aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). 12.2.3.2 external clock the external clock (where available) is selected if cc0=1 and cc1=1 in the cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the exter- nal clock pin extclk that will trigger the free run- ning counter. the counter is synchronised with the falling edge of the internal cpu clock. a minimum of four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the cpu clock frequency. is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + d t other instructions beginning of the sequence sequence completed ls byte ls byte ms byte st72104g, st72215g, st72216g, st72254g 45/140 16-bit timer (cont'd) figure 27. counter timing diagram, internal clock divided by 2 figure 28. counter timing diagram, internal clock divided by 4 figure 29. counter timing diagram, internal clock divided by 8 note: the mcu is in reset state when the internal reset signal is high. when it is low, the mcu is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 st72104g, st72215g, st72216g, st72254g 46/140 16-bit timer (cont'd) 12.2.3.3 input capture in this section, the index, i , may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. the two input capture 16-bit registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition is detected by the icap i pin (see figure 5). the ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). procedure: to use the input capture function, select the fol- lowing in the cr2 register: select the timer clock (cc[1:0]) (see table 13 clock control bits). select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as a floating input). and select the following in the cr1 register: set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as a floating input). when an input capture occurs: the icf i bit is set. the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 31). a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. other- wise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. notes: 1. after reading the ic i hr register, the transfer of input capture data is inhibited and icf i will never be set until the ic i lr register is also read. 2. the ic i r register contains the free running counter value which corresponds to the most recent input capture. 3. the 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. in one pulse mode and pwm mode only the input capture 2 function can be used. 5. the alternate inputs (icap1 & icap2) are always directly connected to the timer. so any transitions on these pins activate the input cap- ture function. moreover if one of the icap i pin is configured as an input and the second one as an output, an interrupt can be generated if the user tog- gles the output pin and if the icie bit is set. this can be avoided if the input capture func- tion i is disabled by reading the ic i hr (see note 1). 6. the tof bit can be used with an interrupt in order to measure events that exceed the timer range (ffffh). ms byte ls byte icir ic i hr ic i lr st72104g, st72215g, st72216g, st72254g 47/140 16-bit timer (cont'd) figure 30. input capture block diagram figure 31. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: a ctive edge is rising edge. st72104g, st72215g, st72216g, st72254g 48/140 16-bit timer (cont'd) 12.2.3.4 output compare in this section, the index, i , may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: assigns pins with a programmable value if the ocie bit is set sets a flag in the status register generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure: to use the output compare function, select the fol- lowing in the cr2 register: set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. select the timer clock (cc[1:0]) (see table 13 clock control bits). and select the following in the cr1 register: select the olvl i bit to applied to the ocmp i pins after the match occurs. set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: ocf i bit is set. the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). a timer interrupt is generated if the ocie bit is set in the cr2 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: d t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 de- pending on cc[1:0] bits, see table 13 clock control bits) if the timer clock is an external clock, the formula is: where: d t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (i.e. clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: write to the oc i hr register (further compares are inhibited). read the sr register (first step of the clearance of the ocf i bit, which may be already set). write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr d oc i r= d t * f cpu presc d oc i r= d t * f ext st72104g, st72215g, st72216g, st72254g 49/140 16-bit timer (cont'd) notes: 1. after a processor write cycle to the oc i hr reg- ister, the output compare function is inhibited until the oc i lr register is also written. 2. if the oc i e bit is not set, the ocmp i pin is a general i/o port and the olvl i bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3. when the timer clock is f cpu /2, ocf i and ocmp i are set while the counter value equals the oc i r register value (see figure 33 on page 53). this behaviour is the same in opm or pwm mode. when the timer clock is f cpu /4, f cpu /8 or in external clock mode, ocf i and ocmp i are set while the counter value equals the oc i r regis- ter value plus 1 (see figure 34 on page 53). 4. the output compare functions can be used both for generating external events on the ocmp i pins even if the input capture mode is also used. 5. the value in the 16-bit oc i r register and the olv i bit should be changed after each suc- cessful comparison in order to control an output waveform or establish a new elapsed timeout. forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. folvl i bits have no effect in either one-pulse mode or pwm mode. figure 32. output compare block diagram output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1 st72104g, st72215g, st72216g, st72254g 50/140 16-bit timer (cont'd) figure 33. output compare timing diagram, f timer =f cpu /2 figure 34. output compare timing diagram, f timer =f cpu /4 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) compare register i latch 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf ocmp i pin (olvl i =1) output compare flag i (ocf i ) st72104g, st72215g, st72216g, st72254g 51/140 16-bit timer (cont'd) 12.2.3.5 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure: to use one pulse mode: 1. load the oc1r register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. select the following in the cr1 register: using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: set the oc1e bit, the ocmp1 pin is then ded- icated to the output compare 1 function. set the opm bit. select the timer clock cc[1:0] (see table 13 clock control bits). then, on a valid event on the icap1 pin, the coun- ter is initialized to fffch and the olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the value fffdh is loaded in the ic1r register. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. the oc1r register value required for a specific timing application can be calculated using the fol- lowing formula: where: t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on the cc[1:0] bits, see table 13 clock control bits) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin (see figure 35). notes: 1. the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. 4. the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5. when one pulse mode is used oc1r is dedi- cated to this mode. nevertheless oc2r and ocf2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the olvl2 level is dedi- cated to one pulse mode. event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc -5 oc i r= t * f ext -5 st72104g, st72215g, st72216g, st72254g 52/140 16-bit timer (cont'd) figure 35. one pulse mode timing example figure 36. pulse width modulation mode timing example counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1 counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r=2ed0h, oc2r=34e2, olvl1=0, olvl2= 1 fffc fffd fffe 2ed0 2ed1 2ed2 st72104g, st72215g, st72216g, st72254g 53/140 16-bit timer (cont'd) 12.2.3.6 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. the pulse width modulation mode uses the com- plete output compare 1 function plus the oc2r register, and so these functions cannot be used when the pwm mode is activated. procedure to use pulse width modulation mode: 1. load the oc2r register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corre- sponding to the period of the pulse if olvl1=0 and olvl2=1, using the formula in the oppo- site column. 3. select the following in the cr1 register: using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc1r register. using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc2r register. 4. select the following in the cr2 register: set oc1e bit: the ocmp1 pin is then dedicat- ed to the output compare 1 function. set the pwm bit. select the timer clock (cc[1:0]) (see table 13 clock control bits). if olvl1=1 and olvl2=0, the length of the posi- tive pulse is the difference between the oc2r and oc1r registers. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on cc[1:0] bits, see table 13 clock control bits) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 36) notes: 1. after a write instruction to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. 2. the ocf1 and ocf2 bits cannot be set by hardware in pwm mode, therefore the output compare interrupt is inhibited. 3. the icf1 bit is set by hardware when the coun- ter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4. in pwm mode the icap1 pin can not be used to perform input capture because it is discon- nected from the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset after each period and icf1 can also generate an interrupt if icie is set. 5. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc -5 oc i r= t * f ext -5 st72104g, st72215g, st72216g, st72254g 54/140 16-bit timer (cont'd) 12.2.4 low power modes 12.2.5 interrupts note: the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chap- ter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 12.2.6 summary of timer modes 1) see note 4 in section 12.2.3.5 oone pulse modeo on page 54 2) see note 5 in section 12.2.3.5 oone pulse modeo on page 54 3) see note 4 in section 12.2.3.6 opulse width modulation modeo on page 56 mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting resumes from the previous count when the mcu is woken up by an interrupt with aexit from halt modeo capability or from the counter reset value when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequent- ly, when the mcu is woken up by an interrupt with aexit from halt modeo capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register. interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie yes no input capture 2 event icf2 yes no output compare 1 event (not available in pwm mode) ocf1 ocie yes no output compare 2 event (not available in pwm mode) ocf2 yes no timer overflow event tof toie yes no modes available resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) yes yes yes yes output compare (1 and/or 2) yes yes yes yes one pulse mode no not recommended 1) no partially 2) pwm mode no not recommended 3) no no st72104g, st72215g, st72216g, st72254g 55/140 16-bit timer (cont'd) 12.2.7 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (cr1) read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no successful comparison. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no suc- cessful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and ocxe is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 st72104g, st72215g, st72216g, st72254g 56/140 16-bit timer (cont'd) control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output com- pare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the internal output compare 1 function of the timer remains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 pin enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output com- pare mode). whatever the value of the oc2e bit, the internal output compare 2 function of the timer remains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bits 3:2 = cc[1:0] clock control. the timer clock mode depends on these bits: table 13. clock control bits note : if the external clock pin is not available, pro- gramming the external clock configuration stops the counter. bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin (extclk) will trigger the counter register. 0: a falling edge triggers the counter register. 1: a rising edge triggers the counter register. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg timer clock cc1 cc0 f cpu /4 0 0 f cpu /2 0 1 f cpu /8 1 0 external clock (where available) 11 st72104g, st72215g, st72216g, st72254g 57/140 16-bit timer (cont'd) status register (sr) read only reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter matches the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) register. bit 5 = tof timer overflow flag. 0: no timer overflow (reset value). 1: the free running counter has rolled over from ffffh to 0000h. to clear this bit, first read the sr register, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter matches the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) register. bit 2-0 = reserved, forced by hardware to 0. input capture 1 high register (ic1hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 icf1 ocf1 tof icf2 ocf2 0 0 0 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb st72104g, st72215g, st72216g, st72254g 58/140 16-bit timer (cont'd) output compare 2 high register (oc2hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the sr register clears the tof bit. alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to sr register does not clear the tof bit in sr register. input capture 2 high register (ic2hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb st72104g, st72215g, st72216g, st72254g 59/140 16-bit timer (cont'd) table 14. 16-bit timer register map and reset values address (hex.) register label 76543210 timer a: 32 timer b: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timer a: 31 timer b: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timer a: 33 timer b: 43 sr reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 - 0 - 0 - 0 timer a: 34 timer b: 44 ichr1 reset value msb - ------ lsb - timer a: 35 timer b: 45 iclr1 reset value msb - ------ lsb - timer a: 36 timer b: 46 ochr1 reset value msb - ------ lsb - timer a: 37 timer b: 47 oclr1 reset value msb - ------ lsb - timer a: 3e timer b: 4e ochr2 reset value msb - ------ lsb - timer a: 3f timer b: 4f oclr2 reset value msb - ------ lsb - timer a: 38 timer b: 48 chr reset value msb 1111111 lsb 1 timer a: 39 timer b: 49 clr reset value msb 1111110 lsb 0 timer a: 3a timer b: 4a achr reset value msb 1111111 lsb 1 timer a: 3b timer b: 4b aclr reset value msb 1111110 lsb 0 timer a: 3c timer b: 4c ichr2 reset value msb - ------ lsb - timer a: 3d timer b: 4d iclr2 reset value msb - ------ lsb - st72104g, st72215g, st72216g, st72254g 60/140 12.3 serial peripheral interface (spi) 12.3.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. the spi is normally used for communication be- tween the microcontroller and external peripherals or another microcontroller. refer to the pin description chapter for the device- specific pin-out. 12.3.2 main features n full duplex, three-wire synchronous transfers n master or slave operation n four master mode frequencies n maximum slave mode frequency = fcpu/2. n four programmable master bit rates n programmable clock polarity and phase n end of transfer interrupt flag n write collision flag protection n master mode fault protection capability. 12.3.3 general description the spi is connected to external devices through 4 alternate pins: miso: master in slave out pin mosi: master out slave in pin sck: serial clock pin ss: slave select pin a basic example of interconnections between a single master and a single slave is illustrated on figure 37. the mosi pins are connected together as are miso pins. in this way data is transferred serially between master and slave (most significant bit first). when the master device transmits data to a slave device via mosi pin, the slave device responds by sending data to the master device via the miso pin. this implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master de- vice via the sck pin). thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. a status flag is used to indicate that the i/o operation is com- plete. four possible data/clock timing relationships may be chosen (see figure 40) but master and slave must be programmed with the same timing mode. figure 37. serial peripheral interface master/slave 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit st72104g, st72215g, st72216g, st72254g 61/140 serial peripheral interface (cont'd) figure 38. serial peripheral interface block diagram dr read buffer 8-bit shift register write read internal bus spi spie spe spr2 mstr cpha spr0 spr1 cpol spif wcol modf serial clock generator mosi miso ss sck control state cr sr - -- -- it request master control st72104g, st72215g, st72216g, st72254g 62/140 serial peripheral interface (cont'd) 12.3.4 functional description figure 37 shows the serial peripheral interface (spi) block diagram. this interface contains 3 dedicated registers: a control register (cr) a status register (sr) a data register (dr) refer to the cr, sr and dr registers in section 12.3.7for the bit definitions. 12.3.4.1 master configuration in a master configuration, the serial clock is gener- ated on the sck pin. procedure select the spr0 & spr1 bits to define the se- rial clock baud rate (see cr register). select the cpol and cpha bits to define one of the four relationships between the data transfer and the serial clock (see figure 40). the ss pin must be connected to a high level signal during the complete byte transmit se- quence. the mstr and spe bits must be set (they re- main set only if the ss pin is connected to a high level signal). in this configuration the mosi pin is a data output and to the miso pin is a data input. transmit sequence the transmit sequence begins when a byte is writ- ten the dr register. the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: the spif bit is set by hardware an interrupt is generated if the spie bit is set and the i bit in the ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set 2. a read to the dr register. note: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read. st72104g, st72215g, st72216g, st72254g 63/140 serial peripheral interface (cont'd) 12.3.4.2 slave configuration in slave configuration, the serial clock is received on the sck pin from the master device. the value of the spr0 & spr1 bits is not used for the data transfer. procedure for correct data transfer, the slave device must be in the same timing mode as the mas- ter device (cpol and cpha bits). see figure 40. the ss pin must be connected to a low level signal during the complete byte transmit se- quence. clear the mstr bit and set the spe bit to as- sign the pins to alternate function. in this configuration the mosi pin is a data input and the miso pin is a data output. transmit sequence the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: the spif bit is set by hardware an interrupt is generated if spie bit is set and i bit in ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set. 2.a read to the dr register. notes: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 12.3.4.6). depending on the cpha bit, the ss pin has to be set to write to the dr register between each data byte transfer to avoid a write collision (see section 12.3.4.4). st72104g, st72215g, st72216g, st72254g 64/140 serial peripheral interface (cont'd) 12.3.4.3 data transfer format during an spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). the serial clock is used to syn- chronize the data transfer during a sequence of eight clock pulses. the ss pin allows individual selection of a slave device; the other slave devices that are not select- ed do not interfere with the spi transfer. clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits. the cpol (clock polarity) bit controls the steady state value of the clock when no data is being transferred. this bit affects both master and slave modes. the combination between the cpol and cpha (clock phase) bits selects the data capture clock edge. figure 40, shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. the ss pin is the slave device select input and can be driven by the master device. the master device applies data to its mosi pin- clock edge before the capture clock edge. cpha bit is set the second edge on the sck pin (falling edge if the cpol bit is reset, rising edge if the cpol bit is set) is the msbit capture strobe. data is latched on the occurrence of the second clock transition. no write collision should occur even if the ss pin stays low during a transfer of several bytes (see figure 39). cpha bit is reset the first edge on the sck pin (falling edge if cpol bit is set, rising edge if cpol bit is reset) is the msbit capture strobe. data is latched on the oc- currence of the first clock transition. the ss pin must be toggled high and low between each byte transmitted (see figure 39). to protect the transmission from a write collision a low value on the ss pin of a slave device freezes the data in its dr register and does not allow it to be altered. therefore the ss pin must be high to write a new data byte in the dr without producing a write collision. figure 39. cpha / ss timing diagram mosi/miso master ss slave ss (cpha=0) slave ss (cpha=1) byte 1 byte 2 byte 3 vr02131a st72104g, st72215g, st72216g, st72254g 65/140 serial peripheral interface (cont'd) figure 40. data clock timing diagram cpol = 1) cpol = 0) miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 cpol = 1 cpol = 0 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) vr02131b msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit sclk (with sclk (with st72104g, st72215g, st72216g, st72254g 66/140 serial peripheral interface (cont'd) 12.3.4.4 write collision error a write collision occurs when the software tries to write to the dr register while a data transfer is tak- ing place with an external device. when this hap- pens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. note: a oread collisiono will never occur since the received data byte is placed in a buffer in which access is always synchronous with the mcu oper- ation. in slave mode when the cpha bit is set: the slave device will receive a clock (sck) edge prior to the latch of the first data transfer. this first clock edge will freeze the data in the slave device dr register and output the msbit on to the exter- nal miso pin of the slave device. the ss pin low state enables the slave device but the output of the msbit onto the miso pin does not take place until the first data transfer clock edge. when the cpha bit is reset: data is latched on the occurrence of the first clock transition. the slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the dr register after its ss pin has been pulled low. for this reason, the ss pin must be high, between each data byte transfer, to allow the cpu to write in the dr register without generating a write colli- sion. in master mode collision in the master device is defined as a write of the dr register while the internal serial clock (sck) is in the process of transfer. the ss pin signal must be always high on the master device. wcol bit the wcol bit in the sr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 41). figure 41. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read sr read dr write dr 2nd step spif =0 wcol=0 spif =0 wcol=0 if no transfer has started wcol=1 if a transfer has started clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 before the 2nd step read sr read dr note: writing in dr register in- stead of reading in it do not reset wcol bit read sr or then then then st72104g, st72215g, st72216g, st72254g 67/140 serial peripheral interface (cont'd) 12.3.4.5 master mode fault master mode fault occurs when the master device has its ss pin pulled low, then the modf bit is set. master mode fault affects the spi peripheral in the following ways: the modf bit is set and an spi interrupt is generated if the spie bit is set. the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read or write access to the sr register while the modf bit is set. 2. a write to the cr register. notes: to avoid any multiple slave conflicts in the case of a system comprising several mcus, the ss pin must be pulled high during the clearing se- quence of the modf bit. the spe and mstr bits may be restored to their original state during or af- ter this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device the modf bit can not be set, but in a multi master configuration the device can be in slave mode with this modf bit set. the modf bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a re- set or default system state using an interrupt rou- tine. 12.3.4.6 overrun condition an overrun condition occurs when the master de- vice has sent several data bytes and the slave de- vice has not cleared the spif bit issuing from the previous data byte transmitted. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the dr register returns this byte. all other bytes are lost. this condition is not detected by the spi peripher- al. st72104g, st72215g, st72216g, st72254g 68/140 serial peripheral interface (cont'd) 12.3.4.7 single master and multimaster configurations there are two types of spi systems: single master system multimaster system single master system a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 42). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written its dr regis- ter. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. multi-master system a multi-master system may also be configured by the user. transfer of master control could be im- plemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the cr register and the modf bit in the sr register. figure 42. single master configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu st72104g, st72215g, st72216g, st72254g 69/140 serial peripheral interface (cont'd) 12.3.5 low power modes 12.3.6 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi operation resumes when the mcu is woken up by an interrupt with aexit from halt modeo capability. interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes no master mode fault event modf yes no st72104g, st72215g, st72216g, st72254g 70/140 serial peripheral interface (cont'd) 12.3.7 register description control register (cr) read/write reset value: 0000xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever spif=1 or modf=1 in the sr register bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss=0 (see section 12.3.4.5 omaster mode faulto on page 70). 0: i/o port connected to pins 1: spi alternate functions connected to pins the spe bit is cleared by reset, so the spi periph- eral is not initially connected to the external pins. bit 5 = spr2 divider enable . this bit is set and cleared by software and it is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 15. 0: divider by 2 enabled 1: divider by 2 disabled bit 4 = mstr master. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss=0 (see section 12.3.4.5 omaster mode faulto on page 70). 0: slave mode is selected 1: master mode is selected, the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are re- versed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the steady state of the serial clock. the cpol bit affects both the master and slave modes. 0: the steady state is a low value at the sck pin. 1: the steady state is a high value at the sck pin. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. bit 1:0 = spr[1 : 0] serial peripheral rate. these bits are set and cleared by software.used with the spr2 bit, they select one of six baud rates to be used as the serial clock when the device is a master. these 2 bits have no effect in slave mode. table 15. serial peripheral baud rate 70 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1 st72104g, st72215g, st72216g, st72254g 71/140 serial peripheral interface (cont'd) status register (sr) read only reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag. this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the cr register. it is cleared by a soft- ware sequence (an access to the sr register fol- lowed by a read or write to the dr register). 0: data transfer is in progress or has been ap- proved by a clearing sequence. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is set, all writes to the dr register are inhibited. bit 6 = wcol write collision status. this bit is set by hardware when a write to the dr register is done during a transmit sequence. it is cleared by a software sequence (see figure 41). 0: no write collision occurred 1: a write collision has been detected bit 5 = unused. bit 4 = modf mode fault flag. this bit is set by hardware when the ss pin is pulled low in master mode (see section 12.3.4.5 omaster mode faulto on page 70). an spi interrupt can be generated if spie=1 in the cr register. this bit is cleared by a software sequence (an ac- cess to the sr register while modf=1 followed by a write to the cr register). 0: no master mode fault detected 1: a fault in master mode has been detected bits 3-0 = unused. data i/o register (dr) read/write reset value: undefined the dr register is used to transmit and receive data on the serial bus. in the master device only a write to this register will initiate transmission/re- ception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. warning: a write to the dr register places data directly into the shift register for transmission. a write to the the dr register returns the value lo- cated in the buffer and not the contents of the shift register (see figure 38 ). 70 spif wcol - modf - - - - 70 d7 d6 d5 d4 d3 d2 d1 d0 st72104g, st72215g, st72216g, st72254g 72/140 serial peripheral interface (cont'd) table 16. spi register map and reset values address (hex.) register label 76543210 0021h spidr reset value msb xxxxxxx lsb x 0022h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0023h spisr reset value spif 0 wcol 00 modf 00000 st72104g, st72215g, st72216g, st72254g 73/140 12.4 i 2 c bus interface (i2c) 12.4.1 introduction the i 2 c bus interface serves as an interface be- tween the microcontroller and the serial i 2 c bus. it provides both multimaster and slave functions, and controls all i 2 c bus-specific sequencing, pro- tocol, arbitration and timing. it supports fast i 2 c mode (400khz). 12.4.2 main features n parallel-bus/i 2 c protocol converter n multi-master capability n 7-bit/10-bit addressing n transmitter/receiver flag n end-of-byte transmission flag n transfer problem detection i 2 c master features: n clock generation n i 2 c bus busy flag n arbitration lost flag n end of byte transmission flag n transmitter/receiver flag n start bit detection flag n start and stop generation i 2 c slave features: n stop bit detection n i 2 c bus busy flag n detection of misplaced start or stop condition n programmable i 2 c address detection n transfer problem detection n end-of-byte transmission flag n transmitter/receiver flag 12.4.3 general description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. the interrupts are enabled or disabled by software. the interface is connected to the i 2 c bus by a data pin (sdai) and by a clock pin (scli). it can be connected both with a standard i 2 c bus and a fast i 2 c bus. this selection is made by soft- ware. mode selection the interface can operate in the four following modes: slave transmitter/receiver master transmitter/receiver by default, it operates in slave mode. the interface automatically switches from slave to master after it generates a start condition and from master to slave in case of arbitration loss or a stop generation, allowing then multi-master ca- pability. communication flow in master mode, it initiates a data transfer and generates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. both start and stop conditions are generated in master mode by software. in slave mode, the interface is capable of recog- nising its own address (7 or 10-bit), and the gen- eral call address. the general call address de- tection may be enabled or disabled by software. data and addresses are transferred as 8-bit bytes, msb first. the first byte(s) following the start con- dition contain the address (one in 7-bit mode, two in 10-bit mode). the address is always transmitted in master mode. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. refer to fig- ure 43. figure 43. i 2 c bus protocol scl sda 12 8 9 msb ack stop start condition condition vr02119b st72104g, st72215g, st72216g, st72254g 74/140 i 2 c bus interface (cont'd) acknowledge may be enabled and disabled by software. the i 2 c interface address and/or general call ad- dress can be selected by software. the speed of the i 2 c interface may be selected between standard (0-100khz) and fast i 2 c (100- 400khz). sda/scl line control transmitter mode: the interface holds the clock line low before transmission to wait for the micro- controller to write the byte in the data register. receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. the scl frequency (f scl ) is controlled by a pro- grammable clock divider which depends on the i 2 c bus mode. when the i 2 c cell is enabled, the sda and scl ports must be configured as floating inputs. in this case, the value of the external pull-up resistor used depends on the application. when the i 2 c cell is disabled, the sda and scl ports revert to being standard i/ o port pins. figure 44. i 2 c interface block diagram data register (dr) data shift register comparator own address registe r 1 (oar1) clock control register (ccr) status register 1 (sr1) control register (cr) control logic status register 2 (sr2) inte rrupt clock control data control scl or scli sda or sdai own address register 2 (oar2) st72104g, st72215g, st72216g, st72254g 75/140 i 2 c bus interface (cont'd) 12.4.4 functional description refer to the cr, sr1 and sr2 registers in section 12.4.7. for the bit definitions. by default the i 2 c interface operates in slave mode (m/sl bit is cleared) except when it initiates a transmit or receive sequence. first the interface frequency must be configured using the fri bits in the oar2 register. 12.4.4.1 slave mode as soon as a start condition is detected, the address is received from the sda line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software). note: in 10-bit addressing mode, the comparision includes the header sequence (11110xx0) and the two most significant bits of the address. header matched (10-bit mode only): the interface generates an acknowledge pulse if the ack bit is set. address not matched : the interface ignores it and waits for another start condition. address matched : the interface generates in se- quence: acknowledge pulse if the ack bit is set. evf and adsl bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister, holding the scl line low (see figure 45 transfer sequencing ev1). next, in 7-bit mode read the dr register to deter- mine from the least significant bit (data direction bit) if the slave must enter receiver or transmitter mode. in 10-bit mode, after receiving the address se- quence the slave is always in receive mode. it will enter transmit mode on receiving a repeated start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1) . slave receiver following the address reception and after sr1 register has been read, the slave receives bytes from the sda line into the dr register via the inter- nal shift register. after each byte the interface gen- erates in sequence: acknowledge pulse if the ack bit is set evf and btf bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister followed by a read of the dr register, holding the scl line low (see figure 45 transfer se- quencing ev2). slave transmitter following the address reception and after sr1 register has been read, the slave sends bytes from the dr register to the sda line via the internal shift register. the slave waits for a read of the sr1 register fol- lowed by a write in the dr register, holding the scl line low (see figure 45 transfer sequencing ev3). when the acknowledge pulse is received: the evf and btf bits are set by hardware with an interrupt if the ite bit is set. closing slave communication after the last data byte is transferred a stop con- dition is generated by the master. the interface detects this condition and sets: evf and stopf bits with an interrupt if the ite bit is set. then the interface waits for a read of the sr2 reg- ister (see figure 45 transfer sequencing ev4). error cases berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and the berr bits are set with an interrupt if the ite bit is set. if it is a stop then the interface discards the data, released the lines and waits for another start condition. if it is a start then the interface discards the data and waits for the next slave address on the bus. af : detection of a non-acknowledge bit. in this case, the evf and af bits are set with an inter- rupt if the ite bit is set. note : in both cases, scl line is not held low; how- ever, sda line can remain low due to possible ?0? bits transmitted last. it is then necessary to release both lines by software. st72104g, st72215g, st72216g, st72254g 76/140 i 2 c bus interface (cont'd) how to release the sda / scl lines set and subsequently clear the stop bit while btf is set. the sda/scl lines are released after the transfer of the current byte. 12.4.4.2 master mode to switch from default slave mode to master mode a start condition generation is needed. start condition setting the start bit while the busy bit is cleared causes the interface to switch to master mode (m/sl bit set) and generates a start condi- tion. once the start condition is sent: the evf and sb bits are set by hardware with an interrupt if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the dr register with the slave address, holding the scl line low (see figure 45 transfer sequencing ev5). slave address transmission then the slave address is sent to the sda line via the internal shift register. in 7-bit addressing mode, one address byte is sent. in 10-bit addressing mode, sending the first byte including the header sequence causes the follow- ing event: the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the dr register, holding the scl line low (see figure 45 transfer se- quencing ev9). then the second address byte is sent by the inter- face. after completion of this transfer (and acknowledge from the slave if the ack bit is set): the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the cr register (for exam- ple set pe bit), holding the scl line low (see fig- ure 45 transfer sequencing ev6). next the master must enter receiver or transmit- ter mode. note: in 10-bit addressing mode, to switch the master to receiver mode, software must generate a repeated start condition and resend the header sequence with the least significant bit set (11110xx1). master receiver following the address transmission and after sr1 and cr registers have been accessed, the master receives bytes from the sda line into the dr reg- ister via the internal shift register. after each byte the interface generates in sequence: acknowledge pulse if if the ack bit is set evf and btf bits are set by hardware with an in- terrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister followed by a read of the dr register, holding the scl line low (see figure 45 transfer se- quencing ev7). to close the communication: before reading the last byte from the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to slave mode (m/sl bit cleared). note: in order to generate the non-acknowledge pulse after the last received data byte, the ack bit must be cleared just before reading the second last data byte. st72104g, st72215g, st72216g, st72254g 77/140 i 2 c bus interface (cont'd) master transmitter following the address transmission and after sr1 register has been read, the master sends bytes from the dr register to the sda line via the inter- nal shift register. the master waits for a read of the sr1 register fol- lowed by a write in the dr register, holding the scl line low (see figure 45 transfer sequencing ev8). when the acknowledge bit is received, the interface sets: evf and btf bits with an interrupt if the ite bit is set. to close the communication: after writing the last byte to the dr register, set the stop bit to gener- ate the stop condition. the interface goes auto- matically back to slave mode (m/sl bit cleared). error cases berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and berr bits are set by hardware with an interrupt if ite is set. af : detection of a non-acknowledge bit. in this case, the evf and af bits are set by hardware with an interrupt if the ite bit is set. to resume, set the start or stop bit. arlo: detection of an arbitration lost condition. in this case the arlo bit is set by hardware (with an interrupt if the ite bit is set and the interface goes automatically back to slave mode (the m/sl bit is cleared). note : in all these cases, the scl line is not held low; however, the sda line can remain low due to possible ?0? bits transmitted last. it is then neces- sary to release both lines by software. st72104g, st72215g, st72216g, st72254g 78/140 i 2 c bus interface (cont'd) figure 45. transfer sequencing legend: s=start, s r = repeated start, p=stop, a=acknowledge, na=non-acknowledge, evx=event (with interrupt if ite=1) ev1: evf=1, adsl=1, cleared by reading sr1 register. ev2: evf=1, btf=1, cleared by reading sr1 register followed by reading dr register. ev3: evf=1, btf=1, cleared by reading sr1 register followed by writing dr register. ev3-1: evf=1, af=1, btf=1; af is cleared by reading sr1 register. btf is cleared by releasing the lines (stop=1, stop=0) or by writing dr register (dr=ffh). note: if lines are released by stop=1, stop=0, the subsequent ev4 is not seen. ev4: evf=1, stopf=1, cleared by reading sr2 register. ev5: evf=1, sb=1, cleared by reading sr1 register followed by writing dr register. ev6: evf=1, cleared by reading sr1 register followed by writing cr register (for example pe=1). ev7: evf=1, btf=1, cleared by reading sr1 register followed by reading dr register. ev8: evf=1, btf=1, cleared by reading sr1 register followed by writing dr register. ev9: evf=1, add10=1, cleared by reading sr1 register followed by writing dr register. 7-bit slave receiver: 7-bit slave transmitter: 7-bit master receiver: 7-bit master transmitter: 10-bit slave receiver: 10-bit slave transmitter: 10-bit master transmitter 10-bit master receiver: s address a data1 a data2 a ..... datan a p ev1 ev2 ev2 ev2 ev4 s address a data1 a data2 a ..... datan na p ev1 ev3 ev3 ev3 ev3-1 ev4 s address a data1 a data2 a ..... datan na p ev5 ev6 ev7 ev7 ev7 s address a data1 a data2 a ..... datan a p ev5 ev6 ev8 ev8 ev8 ev8 s header a address a data1 a ..... datan a p ev1 ev2 ev2 ev4 s r header a data1 a .... . datan a p ev1 ev3 ev3 ev3-1 ev4 s header a address a data1 a ..... datan a p ev5 ev9 ev6 ev8 ev8 ev8 s r header a data1 a .... . datan a p ev5 ev6 ev7 ev7 st72104g, st72215g, st72216g, st72254g 79/140 i 2 c bus interface (cont'd) 12.4.5 low power modes 12.4.6 interrupts figure 46. event flags and interrupt generation note : the i 2 c interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the i-bit in the cc reg- ister is reset (rim instruction). mode description wait no effect on i 2 c interface. i 2 c interrupts cause the device to exit from wait mode. halt i 2 c registers are frozen. in halt mode, the i 2 c interface is inactive and does not acknowledge data on the bus. the i 2 c interface resumes operation when the mcu is woken up by an interrupt with aexit from halt modeo capability. interrupt event event flag enable control bit exit from wait exit from halt 10-bit address sent event (master mode) add10 ite yes no end of byte transfer event btf yes no address matched event (slave mode) adsel yes no start bit generation event (master mode) sb yes no acknowledge failure event af yes no stop detection event (slave mode) stopf yes no arbitration lost event (multimaster configuration) arlo yes no bus error event berr yes no btf adsl sb af stopf arlo berr evf interrupt ite * * evf can also be set by ev6 or an error from the sr2 register. add10 st72104g, st72215g, st72216g, st72254g 80/140 i 2 c bus interface (cont'd) 12.4.7 register description i 2 c control register (cr) read / write reset value: 0000 0000 (00h) bit 7:6 = reserved. forced to 0 by hardware. bit 5 = pe peripheral enable. this bit is set and cleared by software. 0: peripheral disabled 1: master/slave capability notes: when pe=0, all the bits of the cr register and the sr register except the stop bit are reset. all outputs are released while pe=0 when pe=1, the corresponding i/o pins are se- lected by hardware as alternate functions. to enable the i 2 c interface, write the cr register twice with pe=1 as the first write only activates the interface (only pe is set). bit 4 = engc enable general call. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0). the 00h general call address is ac- knowledged (01h ignored). 0: general call disabled 1: general call enabled bit 3 = start generation of a start condition . this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0) or when the start condition is sent (with interrupt generation if ite=1). in master mode: 0: no start generation 1: repeated start generation in slave mode: 0: no start generation 1: start generation when the bus is free bit 2 = ack acknowledge enable. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0). 0: no acknowledge returned 1: acknowledge returned after an address byte or a data byte is received bit 1 = stop generation of a stop condition . this bit is set and cleared by software. it is also cleared by hardware in master mode. note: this bit is not cleared when the interface is disabled (pe=0). in master mode: 0: no stop generation 1: stop generation after the current byte transfer or after the current start condition is sent. the stop bit is cleared by hardware when the stop condition is sent. in slave mode: 0: no stop generation 1: release the scl and sda lines after the cur- rent byte transfer (btf=1). in this mode the stop bit has to be cleared by software. bit 0 = ite interrupt enable. this bit is set and cleared by software and cleared by hardware when the interface is disabled (pe=0). 0: interrupts disabled 1: interrupts enabled refer to figure 46 for the relationship between the events and the interrupt. scl is held low when the add10, sb, btf or adsl flags or an ev6 event (see figure 45) is de- tected. 70 0 0 pe engc start ack stop ite st72104g, st72215g, st72216g, st72254g 81/140 i 2 c bus interface (cont'd) i 2 c status register 1 (sr1) read only reset value: 0000 0000 (00h) bit 7 = evf event flag. this bit is set by hardware as soon as an event oc- curs. it is cleared by software reading sr2 register in case of error event or as described in figure 45. it is also cleared by hardware when the interface is disabled (pe=0). 0: no event 1: one of the following events has occurred: btf=1 (byte received or transmitted) adsl=1 (address matched in slave mode while ack=1) sb=1 (start condition generated in master mode) af=1 (no acknowledge received after byte transmission) stopf=1 (stop condition detected in slave mode) arlo=1 (arbitration lost in master mode) berr=1 (bus error, misplaced start or stop condition detected) add10=1 (master has sent header byte) address byte successfully transmitted in mas- ter mode. bit 6 = add10 10-bit addressing in master mode . this bit is set by hardware when the master has sent the first byte in 10-bit address mode. it is cleared by software reading sr2 register followed by a write in the dr register of the second address byte. it is also cleared by hardware when the pe- ripheral is disabled (pe=0). 0: no add10 event occurred. 1: master has sent first address byte (header) bit 5 = tra transmitter/receiver. when btf is set, tra=1 if a data byte has been transmitted. it is cleared automatically when btf is cleared. it is also cleared by hardware after de- tection of stop condition (stopf=1), loss of bus arbitration (arlo=1) or when the interface is disa- bled (pe=0). 0: data byte received (if btf=1) 1: data byte transmitted bit 4 = busy bus busy . this bit is set by hardware on detection of a start condition and cleared by hardware on detection of a stop condition. it indicates a communication in progress on the bus. this information is still updat- ed when the interface is disabled (pe=0). 0: no communication on the bus 1: communication ongoing on the bus bit 3 = btf byte transfer finished. this bit is set by hardware as soon as a byte is cor- rectly received or transmitted with interrupt gener- ation if ite=1. it is cleared by software reading sr1 register followed by a read or write of dr reg- ister. it is also cleared by hardware when the inter- face is disabled (pe=0). following a byte transmission, this bit is set after reception of the acknowledge clock pulse. in case an address byte is sent, this bit is set only after the ev6 event (see figure 45). btf is cleared by reading sr1 register followed by writ- ing the next byte in dr register. following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ack=1. btf is cleared by reading sr1 register followed by reading the byte from dr register. the scl line is held low while btf=1. 0: byte transfer not done 1: byte transfer succeeded bit 2 = adsl address matched (slave mode). this bit is set by hardware as soon as the received slave address matched with the oar register con- tent or a general call is recognized. an interrupt is generated if ite=1. it is cleared by software read- ing sr1 register or by hardware when the inter- face is disabled (pe=0). the scl line is held low while adsl=1. 0: address mismatched or not received 1: received address matched 70 evf add10 tra busy btf adsl m/sl sb st72104g, st72215g, st72216g, st72254g 82/140 i 2 c bus interface (cont'd) bit 1 = m/sl master/slave. this bit is set by hardware as soon as the interface is in master mode (writing start=1). it is cleared by hardware after detecting a stop condition on the bus or a loss of arbitration (arlo=1). it is also cleared when the interface is disabled (pe=0). 0: slave mode 1: master mode bit 0 = sb start bit (master mode). this bit is set by hardware as soon as the start condition is generated (following a write start=1). an interrupt is generated if ite=1. it is cleared by software reading sr1 register followed by writing the address byte in dr register. it is also cleared by hardware when the interface is disa- bled (pe=0). 0: no start condition 1: start condition generated i 2 c status register 2 (sr2) read only reset value: 0000 0000 (00h) bit 7:5 = reserved. forced to 0 by hardware. bit 4 = af acknowledge failure . this bit is set by hardware when no acknowledge is returned. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while af=1. 0: no acknowledge failure 1: acknowledge failure bit 3 = stopf stop detection (slave mode). this bit is set by hardware when a stop condition is detected on the bus after an acknowledge (if ack=1). an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while stopf=1. 0: no stop condition detected 1: stop condition detected bit 2 = arlo arbitration lost . this bit is set by hardware when the interface los- es the arbitration of the bus to another master. an interrupt is generated if ite=1. it is cleared by soft- ware reading sr2 register or by hardware when the interface is disabled (pe=0). after an arlo event the interface switches back automatically to slave mode (m/sl=0). the scl line is not held low while arlo=1. 0: no arbitration lost detected 1: arbitration lost detected bit 1 = berr bus error. this bit is set by hardware when the interface de- tects a misplaced start or stop condition. an inter- rupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the in- terface is disabled (pe=0). the scl line is not held low while berr=1. 0: no misplaced start or stop condition 1: misplaced start or stop condition bit 0 = gcal general call (slave mode). this bit is set by hardware when a general call ad- dress is detected on the bus while engc=1. it is cleared by hardware detecting a stop condition (stopf=1) or when the interface is disabled (pe=0). 0: no general call address detected on bus 1: general call address detected on bus 70 0 0 0 af stopf arlo berr gcal st72104g, st72215g, st72216g, st72254g 83/140 i 2 c bus interface (cont'd) i 2 c clock control register (ccr) read / write reset value: 0000 0000 (00h) bit 7 = fm/sm fast/standard i 2 c mode. this bit is set and cleared by software. it is not cleared when the interface is disabled (pe=0). 0: standard i 2 c mode 1: fast i 2 c mode bit 6:0 = cc6-cc0 7-bit clock divider. these bits select the speed of the bus (f scl ) de- pending on the i 2 c mode. they are not cleared when the interface is disabled (pe=0). standard mode (fm/sm=0): f scl <= 100khz f scl =f cpu /(2x([cc6..cc0]+2)) fast mode (fm/sm=1): f scl > 100khz f scl =f cpu /(3x([cc6..cc0]+2)) note: the programmed f scl assumes no load on scl and sda lines. i 2 c data register ( dr) read / write reset value: 0000 0000 (00h) bit 7:0 = d7-d0 8-bit data register. these bits contain the byte to be received or trans- mitted on the bus. transmitter mode: byte transmission start auto- matically when the software writes in the dr reg- ister. receiver mode: the first data byte is received au- tomatically in the dr register using the least sig- nificant bit of the address. then, the following data bytes are received one by one after reading the dr register. 70 fm/sm cc6 cc5 cc4 cc3 cc2 cc1 cc0 70 d7 d6 d5 d4 d3 d2 d1 d0 st72104g, st72215g, st72216g, st72254g 84/140 i 2 c bus interface (cont'd) i 2 c own address register (oar1) read / write reset value: 0000 0000 (00h) 7-bit addressing mode bit 7:1 = add7-add1 interface address . these bits define the i 2 c bus address of the inter- face. they are not cleared when the interface is disabled (pe=0). bit 0 = add0 address direction bit. this bit is don't care, the interface acknowledges either 0 or 1. it is not cleared when the interface is disabled (pe=0). note: address 01h is always ignored. 10-bit addressing mode bit 7:0 = add7-add0 interface address . these are the least significant bits of the i 2 c bus address of the interface. they are not cleared when the interface is disabled (pe=0). i 2 c own address register (oar2) read / write reset value: 0100 0000 (40h) bit 7:6 = fr1-fr0 frequency bits. these bits are set by software only when the inter- face is disabled (pe=0). to configure the interface to i 2 c specifed delays select the value corre- sponding to the microcontroller frequency f cpu . bit 5:3 = reserved bit 2:1 = add9-add8 interface address . these are the most significant bits of the i 2 c bus address of the interface (10-bit mode only). they are not cleared when the interface is disabled (pe=0). bit 0 = reserved. 70 add7 add6 add5 add4 add3 add2 add1 add0 70 fr1 fr0 0 0 0 add9 add8 0 f cpu range (mhz) fr1 fr0 2.5 - 6 0 0 6 -10 0 1 10 - 14 1 0 14 - 24 1 1 st72104g, st72215g, st72216g, st72254g 85/140 i c bus interface (cont'd) table 17. i 2 c register map and reset values address (hex.) register label 765 4 3210 0028h i2ccr reset value 0 0 pe 0 engc 0 start 0 ack 0 stop 0 ite 0 0029h i2csr1 reset value evf 0 add10 0 tra 0 busy 0 btf 0 adsl 0 m/sl 0 sb 0 002ah i2csr2 reset value 0 0 0 af 0 stopf 0 arlo 0 berr 0 gcal 0 02bh i2cccr reset value fm/sm 0 cc6 0 cc5 0 cc4 0 cc3 0 cc2 0 cc1 0 cc0 0 02ch i2coar1 reset value add7 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 002dh i2coar2 reset value fr1 0 fr0 1000 add9 0 add8 00 002eh i2cdr reset value msb 000 0 000 lsb 0 st72104g, st72215g, st72216g, st72254g 86/140 12.5 8-bit a/d converter (adc) 12.5.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. the result of the conversion is stored in a 8-bit data register. the a/d converter is controlled through a control/status register. 12.5.2 main features n 8-bit conversion n up to 16 channels with multiplexed input n linear successive approximation n data register (dr) which contains the results n conversion complete status flag n on/off bit (to reduce consumption) the block diagram is shown in figure 1. 12.5.3 functional description 12.5.3.1 analog power supply v dda and v ssa are the high and low level refer- ence voltage pins. in some devices (refer to device pin out description) they are internally connected to the v dd and v ss pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. see electrical characteristics section for more de- tails. figure 47. adc block diagram ch2 ch1 ch3 coco 0 adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux r adc c adc d2 d1 d3 d7 d6 d5 d4 d0 adcdr 4 div 2 f adc f cpu hold control st72104g, st72215g, st72216g, st72254g 87/140 8-bit a/d converter (adc) (cont'd) 12.5.3.2 digital a/d conversion result the conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than or equal to v dda (high-level voltage reference) then the conversion result in the dr register is ffh (full scale) without overflow indication. if input voltage (v ain ) is lower than or equal to v ssa (low-level voltage reference) then the con- version result in the dr register is 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdr register. the accuracy of the conversion is described in the parametric section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 12.5.3.3 a/d conversion phases the a/d conversion is based on two conversion phases as shown in figure 2: n sample capacitor loading [duration: t load ] during this phase, the v ain input voltage to be measured is loaded into the c adc sample capacitor. n a/d conversion [duration: t conv ] during this phase, the a/d conversion is computed (8 successive approximations cycles) and the c adc sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. while the adc is on, these two phases are contin- uously repeated. at the end of each conversion, the sample capaci- tor is kept loaded with the previous measurement load. the advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement. 12.5.3.4 software procedure refer to the control/status register (csr) and data register (dr) in section 0.1.6 for the bit definitions and to figure 2 for the timings. adc configuration the total duration of the a/d conversion is 12 adc clock periods (1/f adc =2/f cpu ). the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the csr register: select the ch[3:0] bits to assign the analog channel to be converted. adc conversion in the csr register: set the adon bit to enable the a/d converter and to start the first conversion. from this time on, the adc performs a continuous conver- sion of the selected channel. when a conversion is complete the coco bit is set by hardware. no interrupt is generated. the result is in the dr register and remains valid until the next conversion has ended. a write to the csr register (with adon set) aborts the current conversion, resets the coco bit and starts a new conversion. figure 48. adc conversion timings 12.5.4 low power modes note : the a/d converter may be disabled by reset- ting the adon bit. this feature allows reduced power consumption when no conversion is needed and between single shot conversions. 12.5.5 interrupts none mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d con- verter requires a stabilisation time before ac- curate conversions can be performed. adccsr write adon coco bit set t load t conv operation hold control st72104g, st72215g, st72216g, st72254g 88/140 8-bit a/d converter (adc) (cont'd) 12.5.6 register description control/status register (csr) read/write reset value: 0000 0000 (00h) bit 7 = coco conversion complete this bit is set by hardware. it is cleared by soft- ware reading the result in the dr register or writing to the csr register. 0: conversion is not complete 1: conversion can be read from the dr register bit 6 = reserved. must always be cleared. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off 1: a/d converter is switched on bit 4 = reserved. must always be cleared. bits 3:0 = ch[3:0] channel selection these bits are set and cleared by software. they select the analog input to convert. *note : the number of pins and the channel selec- tion varies according to the device. refer to the de- vice pinout. data register (dr) read only reset value: 0000 0000 (00h) bits 7:0 = d[7:0] analog converted value this register contains the converted analog value in the range 00h to ffh. note : reading this register reset the coco flag. 70 coco 0 adon 0 ch3 ch2 ch1 ch0 channel pin* ch3 ch2 ch1 ch0 ain0 0 0 0 0 ain1 0 0 0 1 ain2 0 0 1 0 ain3 0 0 1 1 ain4 0 1 0 0 ain5 0 1 0 1 ain6 0 1 1 0 ain7 0 1 1 1 ain8 1 0 0 0 ain9 1 0 0 1 ain10 1 0 1 0 ain11 1 0 1 1 ain12 1 1 0 0 ain13 1 1 0 1 ain14 1 1 1 0 ain15 1 1 1 1 70 d7 d6 d5 d4 d3 d2 d1 d0 st72104g, st72215g, st72216g, st72254g 89/140 8-bit a/d converter (adc) (cont'd) table 18. adc register map and reset values address (hex.) register label 76543210 0070h adcdr reset value d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 0 d0 0 0071h adccsr reset value coco 00 adon 00 ch3 0 ch2 0 ch1 0 ch0 0 st72104g, st72215g, st72216g, st72254g 90/140 13 instruction set 13.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 19. st7 addressing mode overview note 1. at the time the instruction is executed, the program counter (pc) points to the instruction follow- ing jrxx. addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination/ source pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc-128/pc+127 1) +1 relative indirect jrne [$10] pc-128/pc+127 1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 st72104g, st72215g, st72216g, st72254g 91/140 st7 addressing modes (cont'd) 13.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 13.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 13.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 13.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 13.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations st72104g, st72215g, st72216g, st72254g 92/140 st7 addressing modes (cont'd) 13.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 20. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 13.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset follows the opcode. relative (indirect) the offset is defined in memory, of which the ad- dress follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtrac- tion operations bcp bit compare short instructions only functio n clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available relative direct/ indirect instructions function jrxx conditional jump callr call relative st72104g, st72215g, st72216g, st72254g 93/140 13.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four bytes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, di- rect bit, or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruc- tion using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret code condition flag modification sim rim scf rcf st72104g, st72215g, st72216g, st72254g 94/140 instruction groups (cont'd) mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > st72104g, st72215g, st72216g, st72254g 95/140 instruction groups (cont'd) mnemo description function/example dst src h i n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z st72104g, st72215g, st72216g, st72254g 96/140 14 electrical characteristics 14.1 parameter conditions unless otherwise specified, all voltages are re- ferred to v ss . 14.1.1 minimum and maximum values unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25 c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the min- imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 s ). 14.1.2 typical values unless otherwise specified, typical data are based on t a =25 c, v dd =5v (for the 4.5v v dd 5.5v voltage range) and v dd =3.3v (for the 3v v dd 4v voltage range). they are given only as design guidelines and are not tested. 14.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 14.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 49. figure 49. pin loading conditions 14.1.5 pin input voltage the input voltage measurement on a pin of the de- vice is described in figure 50. figure 50. pin input voltage c l st7 pin v in st7 pin st72104g, st72215g, st72216g, st72254g 97/140 14.2 absolute maximum ratings stresses above those listed as aabsolute maxi- mum ratingso may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device under these condi- tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 14.2.1 voltage characteristics 14.2.2 current characteristics 14.2.3 thermal characteristics notes: 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k w for reset, 10k w for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. when the current limitation is not possible, the v in absolute maximum rating must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v dd while a negative injection is induced by v in st72104g, st72215g, st72216g, st72254g 99/140 operating conditions (cont'd) figure 52. f osc maximum operating frequency versus v dd supply voltage for flash devices 2) notes: 1. guaranteed by construction. a/d operation and resonator oscillator start-up are not guaranteed below 1mhz. 2. operating conditions with t a =-40 to +125 c. 3. flash programming tested in production at maximum t a with two different conditions: v dd =5.5v, f cpu =8mhz and v dd =3.2v, f cpu =4mhz. f osc [mhz] supply voltage [v] 16 8 4 1 0 2.5 3.2 3.5 4 4.5 5 5.5 functionali ty funct ionality functionali ty guarantee d in this area 3) not guaran teed in this area not guarantee d in this area with resonato r 1) 3.85 12 functional ity not guarantee d in this area at t a >85 c st72104g, st72215g, st72216g, st72254g 100/140 operating conditions (cont'd) 14.3.2 operating conditions with low voltage detector (lvd) subject to general operating conditions for v dd ,f osc , and t a . figure 53. high lvd threshold versus v dd and f osc for flash devices 3) figure 54. medium lvd threshold versus v dd and f osc for flash devices 3) figure 55. low lvd threshold versus v dd and f osc for flash devices 2)4) notes: 1. lvd typical data are based on t a =25 c. they are given only as design guidelines and are not tested. 2. data based on characterization results, not tested in production. 3. the v dd rise time rate condition is needed to insure a correct device power-on and lvd reset. not tested in production. 4. if the low lvd threshold is selected, when v dd falls below 3.2v, (v dd minimum operating voltage), the device is guar- anteed to continue functioning until it goes into reset state. the specified v dd min. value is necessary in the device power on phase, but during a power down phase or voltage drop the device will function below this min. level. symbol parameter condition s min typ 1) max unit v it+ reset release threshold (v dd rise) high threshold med. threshold low threshold 4.10 2) 3.75 2) 3.25 2) 4.30 3.90 3.35 4.50 4.05 3.55 v v it- reset generation threshold (v dd fall) high threshold med. threshold low threshold 4) 3.85 2) 3.50 2) 3.00 4.05 3.65 3.10 4.30 3.95 3.35 v hyst lvd voltage threshold hysteresis v it+ -v it- 200 250 300 mv vt por v dd rise time rate 3) 0.2 50 v/ms t g(vdd) filtered glitch delay on v dd 2) not detected by the lvd 40 ns f osc [mhz] supply voltage [v] 16 8 0 2.5 3 3.5 4 4.5 5 5.5 functi onal area device under funct ionality and reset not guaranteed in this area for temperatures higher than 85 c reset in this area functi onality not guaran teed in this area v it- 3.85 12 f osc [mhz] supply voltage [v] 16 8 0 2.5 3 v it- 3.5v 4 4.5 5 5.5 functi onal area device under functionali ty and reset not guarantee d in this area for temperatures higher than 85 c reset in this area functi onality not guaran teed in this area 12 f osc [mhz] supply voltage [v] 16 8 0 2.5 v it- 3v 3.5 4 4.5 5 5.5 functi onal area device under functiona lity not guaran teed in this area for temperatures higher than 85 c reset in this area functi onality not guaran teed in this area 12 3.2 see note 4 st72104g, st72215g, st72216g, st72254g 101/140 functional operating conditions (cont'd) figure 56. high lvd threshold versus v dd and f osc for rom devices 2) figure 57. medium lvd threshold versus v dd and f osc for rom devices 2) figure 58. low lvd threshold versus v dd and f osc for rom devices 2)3) notes: 1. lvd typical data are based on t a =25 c. they are given only as design guidelines and are not tested. 2. the minimum v dd rise time rate is needed to insure a correct device power-on and lvd reset. not tested in production. 3. if the low lvd threshold is selected, when v dd falls below 3.2v, the device is guaranteed to be either functioning or under reset. f osc [mhz] supply voltage [v] 16 8 0 2.5 3 3.5 4 4.5 5 5.5 functi onal area device under reset in this area functi onality not guaran teed in this area v it- 3.85 f osc [mhz] supply voltage [v] 16 8 0 2.5 3 v it- 3.5v 4 4.5 5 5.5 functi onal area device under reset in this area functi onality not guaran teed in this area f osc [mhz] supply voltage [v] 16 8 0 2.5 v it- 3.00v 3.5 4 4.5 5 5.5 functi onal area device under reset in this area functi onality not guaran teed in this area st72104g, st72215g, st72216g, st72254g 102/140 14.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to get the total de- vice consumption, the two current values must be added (except for halt mode for which the clock is stopped). 14.4.1 run and slow modes figure 59. typical i dd in run vs. f cpu figure 60. typical i dd in slow vs. f cpu notes: 1. typical data are based on ta=25 c, v dd =5v (4.5v v dd 5.5v range) and vdd=3.4v (3.2v v dd 3.6v range). 2. data based on characterization results, tested in production at v dd max. and f cpu max. 3. cpu running with memory access, all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by external square wave, css and lvd disabled. 4. slow mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by external square wave, css and lvd disabled. symbol parameter conditions max unit d i dd( d ta) supply current variation vs. temperature constant v dd and f cpu 10 % symbol parameter conditions typ 1) max 2) unit i dd supply current in run mode 3) (see figure 59) 4.5v v dd 5.5v f osc =1mhz, f cpu =500khz f osc =4mhz, f cpu =2mhz f osc =16mhz, f cpu =8mhz 500 1500 5600 900 2500 9000 m a supply current in slow mode 4) (see figure 60) f osc =1mhz, f cpu =31.25khz f osc =4mhz, f cpu =125khz f osc =16mhz, f cpu =500khz 150 250 670 450 550 1250 supply current in run mode 3) (see figure 59) 3.2v v dd 3.6v f osc =1mhz, f cpu =500khz f osc =4mhz, f cpu =2mhz f osc =16mhz, f cpu =8mhz 300 970 3600 550 1350 4500 supply current in slow mode 4) (see figure 60) f osc =1mhz, f cpu =31.25khz f osc =4mhz, f cpu =125khz f osc =16mhz, f cpu =500khz 100 170 420 250 300 700 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 1 2 3 4 5 6 7 idd [ma] 8mhz 4mhz 2mhz 500khz 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 idd [ma] 500khz 250khz 125khz 31.25khz st72104g, st72215g, st72216g, st72254g 103/140 supply current characteristics (cont'd) 14.4.2 wait and slow wait modes figure 61. typical i dd in wait vs. f cpu figure 62. typical i dd in slow-wait vs. f cpu notes: 1. typical data are based on t a =25 c, v dd =5v (4.5v v dd 5.5v range) and v dd =3.4v (3.2v v dd 3.6v range). 2. data based on characterization results, tested in production at v dd max. and f cpu max. 3. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by external square wave, css and lvd disabled. 4. slow-wait mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by external square wave, css and lvd disabled. symbol parameter conditions typ 1) max 2) unit i dd supply current in wait mode 3) (see figure 61) 4.5v v dd 5.5v f osc =1mhz, f cpu =500khz f osc =4mhz, f cpu =2mhz f osc =16mhz, f cpu =8mhz 150 560 2200 280 900 3000 m a supply current in slow wait mode 4) (see figure 62) f osc =1mhz, f cpu =31.25khz f osc =4mhz, f cpu =125khz f osc =16mhz, f cpu =500khz 20 90 340 70 190 850 supply current in wait mode 3) (see figure 61) 3.2v v dd 3.6v f osc =1mhz, f cpu =500khz f osc =4mhz, f cpu =2mhz f osc =16mhz, f cpu =8mhz 90 350 1370 200 550 1900 supply current in slow wait mode 4) (see figure 62) f osc =1mhz, f cpu =31.25khz f osc =4mhz, f cpu =125khz f osc =16mhz, f cpu =500khz 10 50 200 20 80 350 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 0.5 1 1.5 2 2.5 3 idd [ma] 8mhz 4mhz 2mhz 500khz 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 idd [ma] 500khz 250khz 125khz 31.25khz st72104g, st72215g, st72216g, st72254g 104/140 supply current characteristics (cont'd) 14.4.3 halt mode 14.4.4 supply and clock managers the previous current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to get the total de- vice consumption, the two current values must be added (except for halt mode). 14.4.5 on-chip peripherals notes: 1. typical data are based on t a =25 c. 2. all i/o pins in input mode with a static value at v dd or v ss (no load), css and lvd disabled. data based on charac- terization results, tested in production at v dd max. and f cpu max. 3. data based on characterization results, not tested in production. 4. data based on characterization results done with the external components specified in section 14.5.3 and section 14.5.4, not tested in production. 5. as the oscillator is based on a current source, the consumption does not depend on the voltage. 6. data based on a differential i dd measurement between reset configuration (timer counter running at f cpu /4) and timer counter stopped (selecting external clock capability). data valid for one timer. 7. data based on a differential i dd measurement between reset configuration and a permanent spi master communica- tion (data sent equal to 55h). 8. data based on a differential i dd measurement between reset configuration and i2c peripheral enabled (pe bit set). 9. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. symbol parameter condition s typ 1) max unit i dd supply current in halt mode 2) v dd =5.5v -40 c t a +85 c 0 10 m a -40 c t a +125 c 150 v dd =3.6v -40 c t a +85 c6 -40 c t a +125 c 100 symbol parameter condit ions typ 1) max 3) unit i dd(ck) supply current of internal rc oscillator 500 750 m a supply current of external rc oscillator 4) 525 750 supply current of resonator oscillator 4) & 5) lp: low power oscillator mp: medium power oscillator ms: medium speed oscillator hs: high speed oscillator 200 300 450 700 400 550 750 1000 clock security system supply current 150 350 i dd(lvd) lvd supply current halt mode 100 150 symbol parameter conditions typ unit i dd(tim) 16-bit timer supply current 6) f cpu =8mhz v dd = 3.4v 50 m a v dd = 5.0v 150 i dd(spi) spi supply current 7) f cpu =8mhz v dd = 3.4v 250 v dd = 5.0v 350 i dd(i2c) i 2 c supply current 8) f cpu =8mhz v dd = 3.4v 250 v dd = 5.0v 350 i dd(adc) adc supply current when converting 9) f adc =4mhz v dd = 3.4v 800 v dd = 5.0v 1100 st72104g, st72215g, st72216g, st72254g 105/140 14.5 clock and timing characteristics subject to general operating conditions for v dd ,f osc , and t a . 14.5.1 general timings 14.5.2 external clock source figure 63. typical application with an external clock source notes: 1. data based on typical application software. 2. time measured between interrupt event and interrupt vector fetch. d t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. 3. data based on design simulation and/or technology characteristics, not tested in production. symbol parameter conditi ons min typ 1) max unit t c(inst) instruction cycle time 2 3 12 t cpu f cpu =8mhz 250 375 1500 ns t v(it) interrupt reaction time 2) t v(it) = d t c(inst) +10 10 22 t cpu f cpu =8mhz 1.25 2.75 m s symbol parameter condi tions min typ max unit v osc1h osc1 input pin high level voltage see figure 63 0.7xv dd v dd v v osc1l osc1 input pin low level voltage v ss 0.3xv dd t w(osc1h) t w(osc1l) osc1 high or low time 3) 15 ns t r(osc1) t f(osc1) osc1 rise or fall time 3) 15 i l oscx input leakage current v ss v in v dd 1 m a osc1 osc2 f osc external st72xxx clock source not connected internally v osc1l v osc1h t r(osc1) t f(osc1) t w(osc1h) t w(osc1l) i l 90% 10% st72104g, st72215g, st72216g, st72254g 106/140 clock and timing characteristics (cont'd) 14.5.3 crystal and ceramic resonator oscillators the st7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. all the information given in this paragraph are based on characterization results with specified typical external components. in the application, the reso- nator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabiliza- tion time. refer to the crystal/ceramic resonator manufacturer for more details (frequency, pack- age, accuracy...). 14.5.3.1 typical crystal resonators figure 64. typical application with a crystal resonator notes: 1. resonator characteristics given by the crystal manufacturer. 2. t su(osc) is the typical oscillator start-up time measured between v dd =2.8v and the fetch of the first instruction (with a quick v dd ramp-up from 0 to 5v (<50 m s). 3. the oscillator selection can be optimized in terms of supply current using an high quality resonator with small r s value. refer to crystal manufacturer for more details. symbol parameter conditio ns min max unit f osc oscillator frequency 3) lp: low power oscillator mp: medium power oscillator ms: medium speed oscillator hs: high speed oscillator 1 >2 >4 >8 2 4 8 16 mhz r f feedback resistor 20 40 k w c l1 c l2 recommended load capacitance ver- sus equivalent serial resistance of the crystal or ceramic resonator (r s ) r s =200 w lp oscillator r s =200 w mp oscillator r s =200 w ms oscillator r s =100 w hs oscillator 38 32 18 15 56 46 26 21 pf i 2 osc2 driving current v dd =5v lp oscillator v in =v ss mp oscillator ms oscillator hs oscillator 40 110 180 400 100 190 360 700 m a option byte config. reference freq. characteristic 1) c l1 [pf] c l2 [pf] t su(osc) [ms] 2) lp jauch s-200-30-30/50 2mhz d f osc =[ 30ppm 25 c , 30ppm d ta ] , typ. r s =200 w 33 34 10~15 mp ss3-400-30-30/30 4mhz d f osc =[ 30ppm 25 c , 30ppm d ta ] , typ. r s =60 w 33 34 7~10 ms ss3-800-30-30/30 8mhz d f osc =[ 30ppm 25 c , 30ppm d ta ] , typ. r s =25 w 33 34 2.5~3 hs ss3-1600-30-30/30 16mhz d f osc =[ 30ppm 25 c , 30ppm d ta ] , typ. r s =15 w 33 34 1~1.5 osc2 osc1 f osc c l1 c l2 i 2 r f st72xxx resonator st72104g, st72215g, st72216g, st72254g 107/140 clock and timing characteristics (cont'd) 14.5.3.2 typical ceramic resonators t su(osc) is the typical oscillator start-up time measured between v dd =2.8v and the fetch of the first instruction (with a quick v dd ramp-up from 0 to 5v (<50 m s). table 21. typical ceramic resonators for general purpose applications notes: 1. murata ceralock (refer to table 23 for correlation factor) 2. v dd 4.5 to 5.5v 3. values in parentheses refer to the capacitors integrated in the resonator symbol parameter conditions typ unit t su(osc) ceramic resonator start-up time lp 2mhz 4.2 ms mp 4mhz 2.1 ms 8mhz 1.1 hs 16mhz 0.7 option byte config. f osc (mhz) resonator part number 1 c l1 [pf] 3 c l2 [pf] 3 r fext [k w ] r d [k w ] lp 1 csb1000j 100 100 open 3.3 csbf1000j 2 csts0200mg06 (47) (47) 0 cstcc2.00mg0h6 mp 2 csts0200mg06 cstcc2.00mg0h6 4 csts0400mg06 cstcc4.00mg0h6 ms 4 csts0400mg06 cstcc4.00mg0h6 8 csts0800mg06 cstcc8.00mg0h6 hs 8 csts0800mg06 cstcc8.00mg0h6 10 csts1000mg03 (15) (15) cstcc10.0mg 12 cst12.0mtw 30 30 cstcv12.0mtj0c4 (22) (22) 16 2 csa16.00mxz040 15 15 cst16.00mxw0c3 (15) (15) csacv16.00mxj040 15 15 10 cstcv16.00mxj0c3 (15) (15) csacw1600mx03 10 10 st72104g, st72215g, st72216g, st72254g 108/140 clock and timing characteristics (cont'd) table 22. typical ceramic resonators for automotive applications notes: 1. murata ceralock (refer to table 23 for correlation factor) 2. v dd 4.5 to 5.5v 3. values in parentheses refer to the capacitors integrated in the resonator figure 65. typical application with ceramic resonator notes: 1. resonator characteristics given by the ceramic resonator manufacturer. 2. t su(osc) is the typical oscillator start-up time measured between v dd =2.8v and the fetch of the first instruction (with a quick v dd ramp-up from 0 to 5v (<50 m s). 3. the oscillator selection can be optimized in terms of supply current using an high quality resonator with small r s value. refer to ceramic resonator manufacturer for more details. option byte config. f osc (mhz) resonator part number 1 c l1 [pf] 3 c l2 [pf] 3 r fext [k w ] r d [k w ] lp 1 csb1000ja 100 100 open 3.3 csbf1000ja 2 csts0200mga06 (47) (47) 0 cstcc2.00mga0h6 mp 2 csts0200mga06 cstcc2.00mga0h6 4 csts0400mga06 cstcc4.00mga0h6 ms 4 csts0400mga06 cstcc4.00mga0h6 8 csts0800mga06 cstcc8.00mga0h6 hs 8 csts0800mga06 cstcc8.00mga0h6 10 csts1000mga03 (15) (15) cstcc10.0mga 12 cst12.0mtwa 30 30 cstcs12.0mta (30) (30) 16 2 csa16.00mxza040 15 15 cst16.00mxwa0c3 (15) (15) csacv16.00mxa040q 15 15 10 cstcv16.00mxa0h3q (15) (15) osc2 osc1 f osc c l1 c l2 i 2 r f st72xxx resonator when resonator with integrate d capaci tors r d r f(ext) st72104g, st72215g, st72216g, st72254g 109/140 clock and timing characteristics (cont'd) table 23. ceramic resonator frequency correlation factor 1 notes: 1. see table 21 and table 22 for ceramic resonator values. option byte config. resonator 1) corre- lation % refer- ence ic option byte config. resonator 1) corre- lation % refer- ence ic lp csb1000j +0.03 4069ube hs csts0800mg06 +0.10 74hcu04 csts0200mg06 -0.16 74hcu04 csts0800mga06 +0.07 cstcc2.00mg0h6 -0.10 cstcc8.00mg0h6 +0.09 mp csts0200mg06 -0.15 csts1000mg03 +0.34 4069ubp cstcc2.00mg0h6 -0.14 cstcc10.0mg +0.75 4069ube csts0400mg06 0.00 cst12.0mtw +0.45 4069ube csts0400mga06 -0.01 cstcv12.0mtj0c4 +0.30 40h004 cstcc4.00mg0h6 -0.02 cstcs12.0mta +0.50 4069ube ms csts0200mg06 -0.15 74hcu04 csa16.00mxz040 +0.10 74hcu04 cstcc2.00mg0h6 -0.14 csacv16.00mxj040 +0.09 csts0400mg06 0.00 csacw1600mx03 +0.03 csts0400mga06 -0.01 csacv16.00mxa040q +0.09 cstcc4.00mg0h6 -0.02 csts0200mg06 -0.15 st72104g, st72215g, st72216g, st72254g 110/140 clock characteristics (cont'd) 14.5.4 rc oscillators the st7 internal clock can be supplied with an rc oscillator. this oscillator can be used with internal or external components (selectable by option byte). figure 66. typical application with rc oscillator figure 67. typical internal rc oscillator figure 68. typical external rc oscillator notes: 1. data based on characterization results. 2. guaranteed frequency range with the specified c ex and r ex ranges taking into account the device process variation. data based on design simulation. 3. data based on characterization results done with v dd nominal at 5v, not tested in production. 4. r ex must have a positive temperature coefficient (ppm/ c), carbon resistors should therefore not be used. 5. important: when no external c ex is applied, the capacitance to be considered is the global parasitic capacitance which is subject to high variation (package, application...). in this case, the rc oscillator frequency tuning has to be done by trying out several resistor values. symbol parameter conditi ons min typ max unit f osc internal rc oscillator frequency 1) see figure 67 3.60 5.10 mhz external rc oscillator frequency 2) 114 t su(osc) internal rc oscillator start-up time 3) 2.0 ms external rc oscillator start-up time 3) r ex =47k w, c ex =o0opf r ex =47k w, c ex =100pf r ex =10k w, c ex =6.8pf r ex =10k w, c ex =470pf 1.0 6.5 0.7 3.0 r ex oscillator external resistor 4) see figure 68 10 47 k w c ex oscillator external capacitor 0 5) 470 pf osc2 osc1 f osc c ex r ex extern al rc internal rc v ref + - v dd current copy voltage generator c ex discharge st72xxx 3.2 5.5 vdd [v] 3.8 3.9 4 4.1 4.2 4.3 fosc [mhz] -40 c +25 c +85 c +125 c 0 6.8 22 47 100 270 470 cex [pf] 0 5 10 15 20 fosc [mhz] rex=10kohm rex=15kohm rex=22kohm rex=33kohm rex=39kohm rex=47kohm st72104g, st72215g, st72216g, st72254g 111/140 clock characteristics (cont'd) 14.5.5 clock security system (css) figure 69. typical safe oscillator frequencies note: 1. data based on characterization results, tested in production between 90khz and 600khz. 2. filtered glitch on the f osc signal. see functional description in section 7.5 on page 23 for more details. symbol parameter conditions min typ max unit f sfosc safe oscillator frequency 1) t a = 25 c, v dd = 5.0v 250 340 550 khz t a = 25 c, v dd = 3.4v 190 260 450 f gfosc glitch filtered frequency 2) 30 mhz 3.2 5.5 vdd [v] 200 250 300 350 400 fosc [khz] -40 c +25 c +85 c +125 c st72104g, st72215g, st72216g, st72254g 112/140 14.6 memory characteristics subject to general operating conditions for v dd ,f osc , and t a unless otherwise specified. 14.6.1 ram and hardware registers 14.6.2 flash program memory notes: 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware reg- isters (only in halt mode). guaranteed by construction, not tested in production. 2. data based on characterization results, tested in production at t a =25 c. 3. up to 16 bytes can be programmed at a time for a 4kbytes flash block (then up to 32 bytes at a time for an 8k device) 4. the data retention time increases when the t a decreases. 5. data based on reliability test results and monitored in production. symbol parameter conditi ons min typ max unit v rm data retention mode 1) halt mode (or reset) 1.6 v symbol parameter conditions min typ max unit t a(prog) programming temperature range 2) 02570 c t prog programming time for 1~16 bytes 3) t a = +25 c825 ms programming time for 4 or 8kbytes t a = +25 c 2.1 6.4 sec t ret data retention 5) t a =+55 c 4) 20 years n rw write erase cycles 5) t a = +25 c 100 cycles st72104g, st72215g, st72216g, st72254g 113/140 14.7 emc characteristics susceptibility tests are performed on a sample ba- sis during product characterization. 14.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the leds). n esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. n ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re- sumed. figure 70. emc recommended star network power supply connection 2) notes: 1. data based on characterization results, not tested in production. 2. the suggested m and 0.1 m f decoupling capacitors on the power supply lines are proposed as a good price vs. emc performance tradeoff. they have to be put as close as possible to the device power supply pins. other emc recommen- dations are given in other sections (i/os, reset, oscx pin characteristics). symbol parameter condition s neg 1) pos 1) unit v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25 c, f osc = 8mhz conforms to iec 1000-4-2 -1 1 kv v fftb fast transient voltage burst limits to be ap- plied through 100pf on v dd and v dd pins to induce a functional disturbance v dd = 5v, t a = +25 c, f osc = 8mhz conforms to iec 1000-4-4 -4 4 v dd v ss 0.1 m f 10 m f v dd st72xxx v ssa v dda 0.1 m f power supply source st7 digital noise filtering external noise filtering st72104g, st72215g, st72216g, st72254g 114/140 emc characteristics (cont'd) 14.7.2 absolute electrical sensitivity based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. for more details, re- fer to the an1181 st7 application note. 14.7.2.1 electro-static discharge (esd) electro-static discharges (3 positive then 3 nega- tive pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends of the number of supply pins of the device (3 parts*(n+1) supply pin). two models are usually simulated: human body model and machine model. this test conforms to the jesd22-a114a/a115a standard. see figure 71 and the following test sequences. human body model test sequence c l is loaded through s1 by the hv pulse gener- ator. s1 switches position from generator to r. a discharge from c l through r (body resistance) to the st7 occurs. s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st7 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. machine model test sequence c l is loaded through s1 by the hv pulse gener- ator. s1 switches position from generator to st7. a discharge from c l to the st7 occurs. s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st7 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. r (machine resistance), in series with s2, en- sures a slow discharge of the st7. absolute maximum ratings figure 71. typical equivalent esd circuits notes: 1. data based on characterization results, not tested in production. symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25 c 2000 v v esd(mm) electro-static discharge voltage (machine model) t a = +25 c 200 st7 s2 r=1500 w s1 high voltage c l = 100pf pulse generator st7 s2 high voltage c l = 200pf pulse generat or r=10k~10m w s1 human body model machine model st72104g, st72215g, st72216g, st72254g 115/140 emc characteristics (cont'd) 14.7.2.2 static and dynamic latch-up n lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable i/o pin) and a power supply switch sequence are performed on each sample. this test conforms to the eia/ jesd 78 ic latch-up standard. for more details, refer to the an1181 st7 application note. n dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards and is described in figure 72. for more details, refer to the an1181 st7 application note. electrical sensitivities figure 72. simplified diagram of the esd generator for dlu notes: 1. class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec spec- ifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). 2. schaffner nsg435 with a pointed test finger. symbol parameter conditions class 1) lu static latch-up class t a = +25 c t a = +85 c a a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25 c a r ch =50m w r d =330 w c s = 150pf esd hv relay dischar ge tip discharge return connection generator 2) st7 v dd v ss st72104g, st72215g, st72216g, st72254g 116/140 emc characteristics (cont'd) 14.7.3 esd pin protection strategy to protect an integrated circuit against electro- static discharge the stress must be controlled to prevent degradation or destruction of the circuit el- ements. the stress generally affects the circuit el- ements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. the elements to be pro- tected must not receive excessive current, voltage or heating within their structure. an esd network combines the different input and output esd protections. this network works, by al- lowing safe discharge paths for the pins subjected to esd stress. two critical esd stress cases are presented in figure 73 and figure 74 for standard pins and in figure 75 and figure 76 for true open drain pins. standard pin protection to protect the output structure the following ele- ments are added: a diode to v dd (3a) and a diode from v ss (3b) a protection device between v dd and v ss (4) to protect the input structure the following ele- ments are added: a resistor in series with the pad (1) a diode to v dd (2a) and a diode from v ss (2b) a protection device between v dd and v ss (4) figure 73. positive stress on a standard pad vs. v ss figure 74. negative stress on a standard pad vs. v dd in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path path to avoid in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path st72104g, st72215g, st72216g, st72254g 117/140 emc characteristics (cont'd) true open drain pin protection the centralized protection (4) is not involved in the discharge of the esd stresses applied to true open drain pads due to the fact that a p-buffer and diode to v dd are not implemented. an additional local protection between the pad and v ss (5a & 5b) is implemented to completely absorb the posi- tive esd discharge. multisupply configuration when several types of ground (v ss ,v ssa , ...) and power supply (v dd ,v dda , ...) are available for any reason (better noise immunity...), the structure shown in figure 77 is implemented to protect the device against esd. figure 75. positive stress on a true open drain pad vs. v ss figure 76. negative stress on a true open drain pad vs. v dd figure 77. multisupply configuration in v dd v ss (1) (2b) (4) out v dd v ss (3b) main path path to avoid (5a) (5b) in v dd v ss (1) (2b) (4) out v dd v ss (3b) main path (3b) (3b) v dda v ssa v dda v dd v ss back to back diode between grounds v ssa st72104g, st72215g, st72216g, st72254g 118/140 14.8 i/o port pin characteristics 14.8.1 general characteristics subject to general operating conditions for v dd ,f osc , and t a unless otherwise specified. figure 78. two typical applications with unused i/o pin figure 79. typical i pu vs. v dd with v in =v ss notes: 1. unless otherwise specified, typical data are based on t a =25 c and v dd =5v. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 4. configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor (see figure 78). data based on design simulation and/or technology characteristics, not tested in production. 5. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteristics de- scribed in figure 79). this data is based on characterization results, tested in production at v dd max. 6. data based on characterization results, not tested in production. 7. to generate an external interrupt, a minimum pulse width has to be applied on an i/o port pin configured as an external interrupt source. symbol parameter conditions min typ 1) max unit v il input low level voltage 2) 0.3xv dd v v ih input high level voltage 2) 0.7xv dd v hys schmitt trigger voltage hysteresis 3) 400 mv i l input leakage current v ss v in v dd 1 m a i s static current consumption 4) floating input mode 200 r pu weak pull-up equivalent resistor 5) v in = v ss v dd =5v 62 120 250 k w v dd =3.4v 170 200 300 c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time 6) c l =50pf between 10% and 90% 25 ns t r(io)out output low to high level rise time 6) 25 t w(it)in external interrupt pulse time 7) 1t cpu 10k w unused i/o port st72xxx 10k w unused i/o port st72xxx v dd 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 10 20 30 40 50 60 70 ipu [ m a] ta=-40 c ta=25 c ta=85 c ta=125 c st72104g, st72215g, st72216g, st72254g 119/140 i/o port pin characteristics (cont'd) 14.8.2 output driving current subject to general operating conditions for v dd ,f osc , and t a unless otherwise specified. figure 80. typical v ol at v dd =5v (standard) figure 81. typical v ol at v dd =5v (high-sink) figure 82. typical v dd -v oh at v dd =5v notes: 1. the i io current sunk must always respect the absolute maximum rating specified in section 14.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect the absolute maximum rating specified in section 14.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins does not have v oh . symbol parameter conditions min max unit v ol 1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 80 and figure 83) v dd =5v i io =+5ma t a 85 c t a 85 c 1.3 1.5 v i io =+2ma t a 85 c t a 85 c 0.65 0.75 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 81 and figure 84) i io =+20ma,t a 85 c t a 85 c 1.5 1.7 i io =+8ma t a 85 c t a 85 c 0.75 0.85 v oh 2) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 82 and figure 85) i io =-5ma, t a 85 c t a 85 c v dd -1.6 v dd -1.7 i io =-2ma t a 85 c t a 85 c v dd -0.8 v dd -1.0 02 46810 iio [ma] 0 0.5 1 1.5 2 2.5 vol [v] at vdd=5v ta=-40 c ta=25 c ta=85 c ta=125 c 0 5 10 15 20 25 30 iio [ma] 0 0.5 1 1.5 2 vol [v] at vdd=5v ta=-40 c ta=25 c ta=85 c ta=125 c -8 -6 -4 -2 0 iio [ma] 1 2 3 4 5 6 vdd-voh [v] at vdd=5v ta=-40 c ta=25 c ta=85 c ta=125 c st72104g, st72215g, st72216g, st72254g 120/140 i/o port pin characteristics (cont'd) figure 83. typical v ol vs. v dd (standard i/os) figure 84. typical v ol vs. v dd (high-sink i/os) figure 85. typical v dd -v oh vs. v dd 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.2 0.25 0.3 0.35 0.4 0.45 0.5 vol [v] at iio=2ma ta=-40 c ta=25 c ta=85 c ta=125 c 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 vol [v] at iio=5ma ta=-40 c ta=25 c ta=85 c ta=125 c 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 vol [v] at iio=8ma ta=-40 c ta=25 c ta=85 c ta=125 c 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.5 0.7 0.9 1.1 1.3 1.5 vol [v] at iio=20ma ta=-40 c ta=25 c ta=85 c ta=125 c 3.5 4 4.5 5 5.5 vdd [v] 0 1 2 3 4 5 vdd-voh [v] at iio=-5ma ta=-40 c ta=25 c ta=85 c ta=125 c 3.2 3.5 4 4.5 5 5.5 vdd [v] 2 2.5 3 3.5 4 4.5 5 5.5 vdd-voh [v] at iio=-2ma ta=-40 c ta=25 c ta=85 c ta=125 c st72104g, st72215g, st72216g, st72254g 121/140 14.9 control pin characteristics 14.9.1 asynchronous reset pin subject to general operating conditions for v dd ,f osc , and t a unless otherwise specified. figure 86. typical application with reset pin 8) notes: 1. unless otherwise specified, typical data are based on t a =25 c and v dd =5v. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 4. the i io current sunk must always respect the absolute maximum rating specified in section 14.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 5. the r on pull-up equivalent resistor is based on a resistive transistor (corresponding i on current characteristics de- scribed in figure 87). this data is based on characterization results, not tested in production. 6. to guarantee the reset of the device, a minimum pulse has to be applied to reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored. 7. the reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy environments. 8. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). symbol parameter condit ions min typ 1) max unit v il input low level voltage 2) 0.3xv dd v v ih input high level voltage 2) 0.7xv dd v hys schmitt trigger voltage hysteresis 3) 400 mv v ol output low level voltage 4) (see figure 88, figure 89) v dd =5v i io =+5ma 0.68 0.95 v i io =+2ma 0.28 0.45 r on weak pull-up equivalent resistor 5) v in = v ss v dd =5v 20 40 60 k w v dd =3.4v 80 100 120 t w(rstl)out generated reset pulse duration external pin or internal reset sources 6 30 1/f sfosc m s t h(rstl)in external reset pulse hold time 6) 20 m s t g(rstl)in filtered glitch duration 7) 100 ns reset v dd watchdog reset st72xxx lvd reset internal r on 0.1 m f v dd 0.1 m f v dd 4.7k w external reset circuit 8) reset control o ption al user st72104g, st72215g, st72216g, st72254g 122/140 control pin characteristics (cont'd) figure 87. typical i on vs. v dd with v in =v ss figure 88. typical v ol at v dd =5v (reset) figure 89. typical v ol vs. v dd (reset) 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 50 100 150 200 ion [ m a] ta=-40 c ta=25 c ta=85 c ta=125 c 012345678 iio [ma] 0 0.5 1 1.5 2 vol [v] at vdd=5v ta=-40 c ta=25 c ta=85 c ta=125 c 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.4 0.6 0.8 1 1.2 vol [v] at iio=5ma ta=-40 c ta=25 c ta=85 c ta=125 c 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.2 0.25 0.3 0.35 0.4 0.45 0.5 vol [v] at iio=2ma ta=-40 c ta=25 c ta=85 c ta=125 c st72104g, st72215g, st72216g, st72254g 123/140 control pin characteristics (cont'd) 14.9.2 ispsel pin subject to general operating conditions for v dd ,f osc , and t a unless otherwise specified. figure 90. two typical applications with ispsel pin 2) notes: 1. data based on design simulation and/or technology characteristics, not tested in production. 2. when the isp remote mode is not required by the application ispsel pin must be tied to v ss . symbol parameter conditio ns min max unit v il input low level voltage 1) v ss 0.2 v v ih input high level voltage 1) v dd -0.1 12.6 i l input leakage current v in =v ss 1 m a ispsel st72xxx 10k w programming tool ispsel st72xxx st72104g, st72215g, st72216g, st72254g 124/140 14.10 timer peripheral characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output...). 14.10.1 watchdog timer 14.10.2 16-bit timer symbol parameter conditions min typ max unit t w(wdg) watchdog time-out duration 12,288 786,432 t cpu f cpu =8mhz 1.54 98.3 ms symbol parameter condit ions min typ max unit t w(icap)in input capture pulse time 1 t cpu t res(pwm) pwm resolution time 2t cpu f cpu =8mhz 250 ns f ext timer external clock frequency 0 f cpu /4 mhz f pwm pwm repetition rate 0 f cpu /4 mhz res pwm pwm resolution 16 bit st72104g, st72215g, st72216g, st72254g 125/140 14.11 communication interface characteristics 14.11.1 spi - serial peripheral interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (ss, sck, mosi, miso). figure 91. spi slave timing diagram with cpha=0 3) notes: 1. data based on design simulation and/or characterisation results, not tested in production. 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends on the i/o port configuration. 3. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol parameter conditio ns min max unit f sck 1/t c(sck) spi clock frequency master f cpu =8mhz f cpu /128 0.0625 f cpu /4 2 mhz slave f cpu =8mhz 0 f cpu /2 4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su(ss) ss setup time slave 120 ns t h(ss) ss hold time slave 120 t w(sckh) t w(sckl) sck high and low time master slave 100 90 t su(mi) t su(si) data input setup time master slave 100 100 t h(mi) t h(si) data input hold time master slave 100 100 t a(so) data output access time slave 0 120 t dis(so) data output disable time slave 240 t v(so) data output valid time slave (after enable edge) 120 t h(so) data output hold time 0 t v(mo) data output valid time master (before capture edge) 0.25 t cpu t h(mo) data output hold time 0.25 ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out see note 2 cpol=0 cpol=1 t su(ss) t h(ss) t dis(so) t h(so) see note 2 bit1 in st72104g, st72215g, st72216g, st72254g 126/140 communication interface characteristics (cont'd) figure 92. spi slave timing diagram with cpha=1 1) figure 93. spi master timing diagram 1) notes: 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha=0 mosi input miso output cpha=0 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol=0 cpol=1 t su(ss) t h(ss) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in ss input sck input cpha=0 mosi output miso input cpha=0 cpha=1 cpha=1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) t v(mo) t h(mo) msb in msb out bit6 in bit6 out lsb out lsb in see note 2 see note 2 cpol=0 cpol=1 cpol=0 cpol=1 t r(sck) t f(sck) st72104g, st72215g, st72216g, st72254g 127/140 communication interface characteristics (cont'd) 14.11.2 i 2 c - inter ic control interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (sdai and scli). the st7 i 2 c interface meets the requirements of the standard i 2 c communication protocol described in the following table. figure 94. typical application with i 2 c bus and timing diagram 4) notes: 1. data based on standard i 2 c protocol requirement, not tested in production. 2. the device must internally provide a hold time of at least 300ns for the sda signal in order to bridge the undefined region of the falling edge of scl. 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. 4. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol parameter standard mode i 2 c fast mode i 2 c unit min 1) max 1) min 1) max 1) t w(scll) scl clock low time 4.7 1.3 m s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 3) 0 2) 900 3) t r(sda) t r(scl) sda and scl rise time 1000 20+0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 20+0.1c b 300 t h(sta) start condition hold time 4.0 0.6 m s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 ns t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 ms c b capacitive load for each bus line 400 400 pf repeated start start stop start t f(sda) t r(sda) t su(sda) t h(sda) t f(sck) t r(sck) t w(sckl) t w(sckh) t h(sta) t su(sto) t su(sta) t w(sto:sta) sda sck 4.7k w sdai st72xxx scli v dd 100 w 100 w v dd 4.7k w i 2 cbus st72104g, st72215g, st72216g, st72254g 128/140 14.12 8-bit adc characteristics subject to general operating conditions for v dd ,f osc , and t a unless otherwise specified. figure 95. typical application with adc notes: 1. unless otherwise specified, typical data are based on t a =25 c and v dd -v ss =5v. they are given only as design guide- lines and are not tested. 2. when v dda and v ssa pins are not available on the pinout, the adc refer to v dd and v ss . 3. any added external serial resistor will downgrade the adc accuracy (especially for resistance greater than 10k w ). data based on characterization results, not tested in production. 4. the stabilization time of the ad converter is masked by the first t load . the first conversion after the enable is then always valid. symbol parameter conditions min typ 1) max unit f adc adc clock frequency 4 mhz v ain conversion range voltage 2) v ssa v dda v r ain external input resistor 10 3) k w c adc internal sample and hold capacitor 6 pf t stab stabilization time after adc enable f cpu =8mhz, f adc =4mhz 0 4) m s t adc conversion time (sample+hold) 3 - sample capacitor loading time - hold conversion time 4 8 1/f adc ainx st72xxx c io ~2pf v dd i l 1 m a v t 0.6v v t 0.6v v ain r ain v dda v ssa 0.1 m f v dd adc st72104g, st72215g, st72216g, st72254g 129/140 8-bit adc characteristics (cont'd) adc accuracy figure 96. adc accuracy characteristics notes: 1. adc accuracy vs. negative injection current: for i inj- =0.8ma, the typical leakage induced inside the die is 1.6 m a and the effect on the adc accuracy is a loss of 1 lsb for each 10k w increase of the external analog source impedance. this effect on the adc accuracy has been observed under worst-case conditions for injection: - negative injection - injection to an input with analog capability, adjacent to the enabled analog input -at5vv dd supply, and worst case temperature. 2. data based on characterization results with t a =25 c. 3. data based on characterization results over the whole temperature range. symbol parameter v dd =5v, 2) f cpu =1mhz v dd =5.0v, 3) f cpu =8mhz v dd =3.3v, 3) f cpu =8mhz unit min max min max min max |e t | total unadjusted error 1) 2.0 2.0 2.0 lsb e o offset error 1) 1.5 1.5 1.5 e g gain error 1) 1.5 1.5 1.5 |e d | differential linearity error 1) 1.5 1.5 1.5 |e l | integral linearity error 1) 1.5 1.5 1.5 e o e g 1 lsb ideal 1lsb ideal v dda v ssa 256 ---------------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 255 254 253 5 4 3 2 1 0 7 6 1234567 253 254 255 256 (1) (2) e t e d e l (3) v dda v ssa st72104g, st72215g, st72216g, st72254g 130/140 15 package characteristics 15.1 package mechanical data figure 97. 32-pin shrink plastic dual in line package figure 98. 28-pin plastic small outline package, 300-mil width dim. mm inches min typ max min typ max a 3.56 3.76 5.08 0.140 0.148 0.200 a1 0.51 0.020 a2 3.05 3.56 4.57 0.120 0.140 0.180 b 0.36 0.46 0.58 0.014 0.018 0.023 b1 0.76 1.02 1.40 0.030 0.040 0.055 c 0.20 0.25 0.36 0.008 0.010 0.014 d 27.43 27.94 28.45 1.080 1.100 1.120 e 9.91 10.41 11.05 0.390 0.410 0.435 e1 7.62 8.89 9.40 0.300 0.350 0.370 e 1.78 0.070 ea 10.16 0.400 eb 12.70 0.500 l 2.54 3.05 3.81 0.100 0.120 0.150 number of pins n32 1 n b d vr01725j n/2 b1 e a l see lead detail e 1 e 3 a 2 a 1 e c e b e a dim. mm inches min typ max min typ max a 2.35 2.65 0.0926 0.1043 a1 0.10 0.30 0.0040 0.0118 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.0091 0.0125 d 17.70 18.10 0.6969 0.7125 e 7.40 7.60 0.2914 0.2992 e 1.27 0.0500 h 10.01 10.64 0.394 0.419 h 0.25 0.74 0.010 0.029 k 0 8 l 0.41 1.27 0.016 0.050 g 0.10 0.004 number of pins n28 so28 st72104g, st72215g, st72216g, st72254g 131/140 15.2 thermal characteristics notes: 1. the power dissipation is obtained from the formula p d =p int +p port where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipation determined by the user. 2. the average chip-junction temperature can be obtained from the formula t j =t a +p d x rthja. symbol ratings value unit r thja package thermal resistance (junction to ambient) sdip32 so28 60 75 c/w p d power dissipation 1) 500 mw t jmax maximum junction temperature 2) 150 c st72104g, st72215g, st72216g, st72254g 132/140 15.3 soldering and glueability information recommended soldering information given only as design guidelines in figure 99 and figure 100. recommended glue for smd plastic packages dedicated to molding compound with silicone: n heraeus: pd945, pd955 n loctite: 3615, 3298 figure 99. recommended wave soldering profile (with 37% sn and 63% pb) figure 100. recommended reflow soldering oven profile (mid jedec) 250 200 150 100 50 0 40 80 120 160 time [sec] temp. [ c] 20 60 100 140 5 sec cooling phase (room temperature) preheating 80 c phase soldering phase 250 200 150 100 50 0 100 200 300 400 time [sec] temp. [ c] ramp up 2 c/sec for 50sec 90 sec at 125 c 150 sec above 183 c ramp down natural 2 c/sec max tmax=220+/-5 c for 25 sec st72104g, st72215g, st72216g, st72254g 133/140 16 device configuration and ordering information each device is available for production in user pro- grammable versions (flash) as well as in factory coded versions (rom). flash devices are shipped to customers with a default content (ffh), while rom factory coded parts contain the code supplied by the customer. this implies that flash devices have to be configured by the customer us- ing the option bytes while the rom devices are factory-configured. 16.1 option bytes the two option bytes allow the hardware configu- ration of the microcontroller to be selected. the option bytes have no address in the memory map and can be accessed only in programming mode (for example using a standard st7 program- ming tool). the default content of the flash is fixed to ffh. in masked rom devices, the option bytes are fixed in hardware by the rom code (see option list). user option byte 0 bit 7:2 = reserved , must always be 1. bit 1 = extit external interrupt configuration . this option bit allows the external interrupt map- ping to be configured as shown in table 24. table 24. external interrupt configuration bit 0 = fmp full memory protection. this option bit enables or disables external access to the internal program memory (read-out protec- tion). clearing this bit causes the erasing (to 00h) of the whole memory (including the option byte). 0: program memory not read-out protected 1: program memory read-out protected user option byte 1 bit 7 = cfc clock filter control on/off this option bit enables or disables the clock filter (cf) features. 0: clock filter enabled 1: clock filter disabled bit 6:4 = osc[2:0] oscillator selection these three option bits can be used to select the main oscillator as shown in table 25. bit 3:2 = lvd[1:0] low voltage detection selection these option bits enable the lvd block with a se- lected threshold as shown in table 26. bit 1 = wdg halt watchdog and halt mode this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode bit 0 = wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) table 25. main oscillator configuration table 26. lvd threshold configuration external it0 external it1 extit ports pa7-pa0 ports pb7-pb0 ports pc5-pc0 1 ports pa7-pa0 ports pc5-pc0 ports pb7-pb0 0 selected oscillator osc2 osc1 osc0 external clock (stand-by) 111 ~4 mhz internal rc 110 1~14 mhz external rc 10x low power resonator (lp) 011 medium power resonator (mp) 010 medium speed resonator (ms) 001 high speed resonator (hs) 000 configuratio n lvd1 lvd0 lvd off 11 highest voltage threshold ( ~ 4.50v) 10 medium voltage threshold ( ~ 4.05v) 01 lowest voltage threshold ( ~ 3.45v) 00 user option byte 0 70 user option byte 1 70 reserved extit fmp cfc osc 2 osc 1 osc 0 lvd1 lvd0 wdg halt wdg sw default value 111111 1 011101111 st72104g, st72215g, st72216g, st72254g 134/140 16.2 device ordering information and transfer of customer code customer code is made up of the rom contents and the list of the selected options (if any). the rom contents are to be sent on diskette, or by electronic means, with the s19 hexadecimal file generated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to stmicroelectronics using the correctly completed option list appended. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. figure 101. rom factory coded device types figure 102. flash user programmable device types device package temp. range xxx / code name (defined by stmicroelectronics) 1 = standard 0 to +70 c 5 = extended -10 to +85 c 6 = industrial -40 to +85 c 7 = automotive -40 to +105 c 3 = automotive -40 to +125 c b= plastic dip m= plastic soic st72104g1, st72104g2, st72215g2, st72216g1, st72254g1, st72254g2 device package temp. range 1= standard 0 to +70 c 5 = extended -10 to +85 c 6= industrial -40 to +85 c 7= automotive -40 to +105 c 3 = automotive -40 to +125 c b= plastic dip m= plastic soic st72c104g1, st72c104g2, st72c215g2, st72c216g1, st72104g, st72215g, st72216g, st72254g 135/140 transfer of customer code (cont'd) microcontroller option list customer . . . . . . . . . . . . . . . ..................... ................................. address . . . . . . . . . . . . . . . ..................... ................................. ..................................................................... contact . . . . . . . . . . . . . . . ..................... ................................. phone no . . . . . . . . . . . . . . . ..................... ................................. reference . . . . . . . . . . . . . . . ..................... ................................. device: [ ] st72104g1 (4kb) [ ] st72215g2 (4kb) [ ] st72254g1 (4kb) [ ] st72104g2 (8kb) [ ] st72216g1 (8kb) [ ] st72254g2 (8kb) package: [ ] so28 [ ] tape & reel [ ] tube [ ] sdip32 marking: [ ] standard marking [ ] special marking so28 (max. 13 chars.): _ _ ___________ sdip32 (max. 15 chars. ): _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ authorized characters are letters, digits, `.', `-', `/' and spaces only. please consult your lo- cal stmicroelectronics sales office for other marking details if required. external interrupt: [ ] it0 interrupt vector port a, it1 interrupt vector port b & c [ ] it0 interrupt vector port a & c, it1 interrupt vector port b temperature range: [ ] 0 cto+70 c[]-10 cto+85 c []-40 cto+85 c[]-40 cto+105 c[]-40 c to + 125 c clock source selection: [ ] resonator: [ ] lp: low power resonator (1 to 2 mhz) [ ] mp: medium power resonator (2 to 4 mhz) [ ] ms: medium speed resonator (4 to 8 mhz) [ ] hs: high speed resonator (8 to 16 mhz) [ ] rc network: [ ] internal [ ] external [ ] external clock clock security system: [ ] disabled [ ] enabled watchdog selection: [ ] software activation [ ] hardware activation halt when watchdog on: [ ] reset [ ] no reset readout protection: [ ] disabled [ ] enabled lvd reset [ ] disabled [ ] enabled: [ ] highest threshold [ ] medium threshold [ ] lowest threshold comments : .................... ............................................ .......... supply operating range in the application: . . . . . . . . . . . . ...................................... notes: . . . . ............................ .......................................... signature: . . . . ............................ .......................................... st72104g, st72215g, st72216g, st72254g 136/140 16.3 development tools stmicroelectronics offers a range of hardware and software development tools for the st7 micro- controller family. full details of tools available for the st7 from third party manufacturers can be ob- tain from the stmicroelectronics internet site: ? http//mcu.st.com. third party tools n actum n bp n cosmic n cmx n data i/o n hitex n hiware n isystem n kanda n leap tools from these manufacturers include c compli- ers, emulators and gang programmers. stmicroelectronics tools three types of development tool are offered by st, all of them connect to a pc via a parallel (lpt) port: see table 27 and table 28 for more details. table 27. stmicroelectronics tool features table 28. dedicated stmicroelectronics development tools note : 1. in-situ programming (isp) interface for flash devices. in-circuit emulation programming capabili ty 1) software included st7 development kit yes. (same features as hds2 emulator but without logic analyzer) yes (dip packages only) st7 cd rom with: st7 assembly toolchain stvd7 and wgdb7 powerful source level debugger for win 3.1, win 95 and nt c compiler demo versions st realizer for win 3.1 and win 95. windows programming tools for win 3.1, win 95 and nt st7 hds2 emulator yes, powerful emulation features including trace/ logic analyzer no st7 programming board no yes (all packages) suppor ted products st7 development kit st7 hds2 emulator st7 programming board st72254g1, ST72C254G1 st72254g2, ST72C254G2 st72215g2, st72c215g2 st72216g1, st72c216g1 st72104g1, st72c104g1, st72104g2, st72c104g2 st7mdt1-dvp2 st7mdt1-emu2b st7mdt1-epb2/eu st7mdt1-epb2/us st7mdt1-epb2/uk st72104g, st72215g, st72216g, st72254g 137/140 development tools (cont'd) 16.3.1 package/socket footprint proposal table 29. suggested list of sdip32 socket types table 30. suggested list of so28 socket types package / probe adaptor / socket reference same footp rint socket type sdip32 emu probe textool 232-1291-00 x textool package / probe adaptor / socket reference same footp rint socket type so28 enplas ots-28-1.27-04 open top yamaichi ic51-0282-334-1 clamshell emu probe adapter from so28 to sdip32 footprint (delivered with emulator) x smd to sdip st72104g, st72215g, st72216g, st72254g 138/140 16.4 st7 application notes 16.5 to get more information to get the latest information on this product please use the st web server: http://mcu.st.com/ identification description programming and tools an985 executing code in st7 ram an986 using the st7 indirect addressing mode an987 st7 in-circuit programming an988 starting with st7 assembly tool chain an989 starting with st7 hiware c an1039 st7 math utility routines an1064 writing optimized hiware c language for st7 an1106 translating assembly code from hc05 to st7 example drivers an969 st7 sci communication between the st7 and a pc an970 st7 spi communication between the st7 and e prom an971 st7 i c communication between the st7 and e prom an972 st7 software spi master communication an973 sci software communication with a pc using st72251 16-bit timer an974 real time clock with the st7 timer output compare an976 driving a buzzer using the st7 pwm function an979 driving an analog keyboard with the st7 adc an980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 usb microcontroller an1041 using st7 pwm signal to generate analog output (sinusoid) an1042 st7 routine for i c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 software implementation of i c bus master an1046 st7 uart emulation software an1047 managing reception errors with the st7 sci peripheral an1048 st7 software lcd driver an1078 st7 timer pwm duty cycle switch for true 0% or 100% duty cycle an1082 description of the st72141 motor control an1083 st72141 bldc motor control softw are and flowchart example an1129 pwm management for bldc motor drives using the st72141 an1130 brushless dc motor drive with st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1182 using the st7 usb low-speed firmware product optimization an982 using ceramic resonators with the st7 an1014 how to minimize the st7 power consumption an1070 st7 checksum selfchecking capability an1179 programming st7 flash microcontrollers in remote isp product evaluation an910 st7 and st9 performance benchmarking an990 st7 benefits versus industry standard an1086 st7 / st10u435 can-do solutions for car multiplexing an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f8 st72104g, st72215g, st72216g, st72254g 139/140 17 summary of changes description of the changes between the current release of the specification and the previous one. rev. main changes date 2.6 added one temperature range (-10 cto+85 c) nov-00 st72104g, st72215g, st72216g, st72254g 140/140 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain sweden - switzerland - united kingdom - u.s.a. http:// www.st.com |
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